Apparatus and method for timestamping of data packets

Patent metadata

Field	Value
Publication number	US-2016337114-A1
Application number	US-201615150979-A
Country	US
Kind code	A1
Filing date	May 10, 2016
Priority date	May 15, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

An apparatus and method for timestamping data packets are provided. The apparatus includes an input bit counter responsive to input bits entering a physical layer (PHY) device and an output bit counter responsive to output bits transmitted by the PHY device. A timestamp for an incoming bit is calculated based on a number of bits awaiting transmission by the PHY device at the time of arrival of the incoming bit. The number of bits awaiting transmission by the PHY device is determined based on the first count and the second count.

First claim

What is claimed is:

1 . A communications device, comprising:
an input bit counter configured to maintain a first count responsive to input bits received by a physical layer (PHY) device from a media access control (MAC) sublayer; an output bit counter configured to maintain a second count responsive to output bits transmitted by the PHY device onto a physical medium; and control circuitry configured to:
upon receipt, by the PHY device from the MAC sublayer, of a first bit of a data packet, determine a number of bits awaiting transmission by the PHY device onto the physical medium based on the first count and the second count; and
calculate a timestamp for the data packet based on the determined number of bits and a pre-determined bit transmission rate of the PHY device.

2 . The communications device of claim 1 , wherein the control circuitry is configured to subtract the second count from the first count to determine the number of bits awaiting transmission by the PHY device onto the physical medium.

3 . The communications device of claim 1 , wherein the control circuitry is configured to:
divide the determined number of bits by the pre-determined bit transmission rate of the PHY device to determine a PHY latency for the first bit of the data packet; and add the determined PHY latency to a current clock time to determine the timestamp for the data packet.

4 . The communications device of claim 1 , wherein the timestamp represents the time of transmission of the first bit of the data packet by the PHY device onto the physical medium, and wherein the control circuitry is further configured to insert the timestamp into a timestamp field of the data packet.

5 . The communications device of claim 1 , wherein the input bits include a data block having a pre-defined number of bits, and wherein the control circuitry is further configured to:
determine a number of overhead bits that are added to the pre-defined number of bits of the data block due to processing by the PHY device before transmission onto the physical medium; and control the input bit counter to increment the first count by the pre-defined number of bits of the data block adjusted by the number of overhead bits.

6 . The communications device of claim 5 , wherein the number of overhead bits is responsive to one or more of: line encoding bits added to the data block, alignment marker insertion bits added to the data block, Forward Error Correction (FEC) compression bits removed from the data block, and FEC parity bits added to the data block.

7 . The communications device of claim 1 , wherein the PHY device includes a plurality of transmission lanes, and wherein the input bit counter and the output bit counter correspond to a first transmission lane of the plurality of transmission lanes.

8 . The communications device of claim 1 , wherein the input bit counter and the output bit counter are associated with different clock domains, the control circuitry further configured to:
compute a cross-domain transfer time error associated with transferring one or more of the first count and the second count to another clock domain; and determine the number of bits awaiting transmission by the PHY device using the computed cross-domain transfer time error.

9 . A method of timestamping data packets, comprising:
receiving, by a physical layer (PHY) device, a data block from a media access control (MAC) sublayer; on condition that a first bit of the data block corresponds to a first bit of a data packet,
determining a number of bits awaiting transmission by the PHY device onto a physical medium based on a first count and a second count, the first count responsive to a number of input bits that entered the PHY device, and the second count responsive to a number of bits transmitted by the PHY device onto the physical medium; and
calculating a timestamp for the data packet based on the determined number of bits awaiting transmission by the PHY device;
incrementing the first count responsive to receiving the data block; and incrementing the second count upon transmission of the data block onto the physical medium.

10 . The method of claim 9 , wherein determining the number of bits awaiting transmission by the PHY device onto the physical medium comprises subtracting the second count from the first count.

11 . The method of claim 9 , further comprising:
dividing the determined number of bits by a pre-determined bit transmission rate of the PHY device to determine a PHY latency for the first bit of the data packet; and adding the determined PHY latency to a current clock time to calculate the timestamp for the data packet.

12 . The method of claim 9 , wherein the timestamp represents the time of transmission of the first bit of the data packet by the PHY device onto the physical medium, the method further comprising:
inserting the timestamp into a timestamp field of the data packet.

13 . The method of claim 9 , wherein the data block includes a pre-defined number of bits, the method further comprising:
determining a number of overhead bits that are added to the pre-defined number of bits of the data block due to processing of the data block by the PHY device before transmission onto the physical medium, and wherein incrementing the first count responsive to receiving the data block comprises incrementing the first count by the pre-defined number of bits of the data block adjusted by the number of overhead bits.

14 . The method of claim 13 , wherein the number of overhead bits is responsive to one or more of: line encoding bits added to the data block, alignment marker insertion bits added to the data block, Forward Error Correction (FEC) compression bits removed from the data block, and FEC parity bits added to the data block.

15 . A communications device, comprising:
a physical layer (PHY) device having an input port and an output port, the input port being configured to receive data from a physical medium; and control circuitry configured to:
generate a first timestamp for a first bit of a beat of data upon generation of the first bit by the PHY device on the output port; and
when the beat of data includes a first bit of a data packet,
determine a bit shift of the first bit of the data packet from the first bit of the beat of data; and
calculate a second timestamp for the first bit of the data packet based on the first timestamp and the determined bit shift.

16 . The communications device of claim 15 , wherein the control circuitry is further configured to:
determine whether the beat of data includes a boundary bit of a data block; and when the beat of data includes the boundary bit of the data block, determine a third timestamp for the boundary bit based on the first timestamp and a bit location of the boundary bit within the beat of data.

17 . The communications device of claim 16 , wherein the control circuitry is further configured to:
determine whether the data block corresponds to a first data block of the data packet; and when the data block corresponds to the first data block of the data packet, set the bit shift of the first bit of the data packet as equal to the bit location of the boundary bit within the beat of data.

18 . The communications device of claim 17 , wherein the control circuitry is further configured to calculate a first latency required to receive, by the PHY device, bits preceding the boundary bit within the beat of data based on the bit location of the boundary bit within the beat of data.

Assignees

• Broadcom Corp

Inventors

• Baden Eric
• Bansal Ankit
• Gargeshwari Sharath

Classifications

• H04J3/0661

  using timestamps · CPC title

• H04L43/0894

  Packet rate · CPC title

• H04J3/0697 Primary

  Synchronisation in a packet node · CPC title

• H04L69/28

  Timers or timing mechanisms used in protocols · CPC title

• H04L43/0852

  Delays · CPC title