Clock data recovery apparatus and method and phase detector

Patent metadata

Field	Value
Publication number	US-9685962-B2
Application number	US-201615207855-A
Country	US
Kind code	B2
Filing date	Jul 12, 2016
Priority date	Sep 4, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.

First claim

What is claimed is:

1. A clock data recovery apparatus, comprising:
an oscillator, generating an original clock signal;
a phase detector, comprising:
a first sampling circuit, sampling a data signal using the original clock signal to generate a first set of sample results;
a frequency dividing circuit, receiving the original clock signal and dividing a frequency of the original clock signal to generate a frequency divided clock signal;
a second sampling circuit, performing sampling using the frequency divided clock signal to generate a second set of sample results; and
a selecting circuit, selectively outputting one of the first set of sample results and the second set of sample results as a final set of sample results; and

an oscillator control circuit, controlling the oscillator according to the final set of sample results.

2. The clock data recovery apparatus according to claim 1 , wherein the second sampling circuit samples a set of sample results, generated according to the data signal, using the frequency divided clock signal to generate the second set of sample results.

3. The clock data recovery apparatus according to claim 1 , wherein the second sampling circuit samples the first set of sample results using the frequency divided clock signal to generate the second set of sample results.

4. The clock data recovery apparatus according to claim 1 , wherein the second sampling circuit samples the data signal using the frequency divided clock signal to generate the second set of sample results.

5. The clock data recovery apparatus according to claim 1 , wherein the selecting circuit determines to output the first set of sample results or the second set of sample results according to a transmission rate of the data signal.

6. The clock data recovery apparatus according to claim 1 , wherein the first sampling circuit comprises four sampling sub-circuits that sample the data signal using four state transition points of the original clock signal, respectively, to generate four sample results as the first set of sample results; phase differences between any one of the four state transition points and the other three state transition points are 90°, 180° and 270°, respectively; when a transmission rate of the data signal is twice a frequency of the original clock signal, the selecting circuit outputs the first set of sample results.

7. The clock data recovery apparatus according to claim 1 , wherein when the selecting circuit selects to output the first set of sample results, at least one of the frequency dividing circuit and the second sampling circuit is disabled.

8. The clock data recovery apparatus according to claim 1 , wherein the second sampling circuit comprises:
a first sampling sub-circuit, performing sampling using a plurality of rising edges of the frequency divided clock signal to generate an intermediate sample result;
a second sampling sub-circuit, sampling the intermediate sample result using a plurality of falling edges of the frequency divided clock signal to generate a first part of the second set of sample results; and
a third sampling sub-circuit, performing sampling using a plurality of falling edges of the frequency divided clock signal to generate a second part of the second set of sample results.

9. A phase detector, comprising:
a frequency dividing circuit, dividing a frequency of an original clock signal to generate (N−1) frequency divided signals having different frequencies, where N is a positive integer greater than 1; and
N sampling circuits, generating N sets of sample results; a first sampling circuit in the N sampling circuits sampling a data signal using the original clock signal to generate a first set of sample results in the N sets of sample results;
an ith sampling circuit in the N sampling circuits receiving an (i−1)th frequency divided signal from the frequency dividing circuit, and sampling the (i−1)th set of sample results using the (i−1)th frequency divided clock signal to generate an ith set of sample results, where i is an integer index ranging between 2 and N.

10. The phase detector according to claim 9 , further comprising:
a selecting circuit, selectively outputting a set of sample results in the N sets of sample results according to a transmission rate of the data signal.

11. The phase detector according to claim 10 , wherein the first sampling circuit comprises four sampling sub-circuits that sample the data signal using four state transition points of the original clock signal, respectively, to generate four first sample results as the first set of sample results; phase differences between any one of the four state transition points and the other three state transition points are 90°, 180° and 270°, respectively; when a transmission rate of the data signal is twice a frequency of the original clock signal, the selecting circuit outputs the first set of sample results.

12. The phase detector according to claim 10 , wherein when the selecting circuit selects to output the (i−1)th set of sample results, the ith sampling circuit to the Nth sampling circuit in the N sampling circuits are disabled.

13. The phase detector according to claim 9 , wherein the ith sampling circuit comprises:
a first sampling sub-circuit, sampling the data signal or the (i−1)th set of sample results using a plurality of rising edges of the (i−1)th frequency divided clock signal to generate an intermediate sample result;
a second sampling sub-circuit, sampling the intermediate sample result using a plurality of falling edges of the (i−1)th frequency divided clock signal to generate a first part of the ith set of sample results; and
a third sampling sub-circuit, sampling the data signal or the (i−1)th set of sample results using a plurality of falling edges of the (i−1)th frequency divided clock signal to generate a second part of the ith set of sample results.

14. A clock data recovery method, comprising:
receiving a data signal and an original clock signal;
sampling the data signal using the original clock signal to generate a first set of sample results;
dividing a frequency of the original clock signal to generate a frequency divided clock signal;
performing sampling using the frequency divided clock signal to generate a second set of sample results; and
adjusting the original clock signal selectively according to one of the first set of sample results and the second set of sample results.

15. The clock data recovery method according to claim 14 , wherein the step of performing sampling using the frequency divided clock signal to generate the second set of sample results comprises:
sampling a set of sample results generated according to the data signal using the frequency divided clock signal to generate the second set of sample results.

16. The clock data recovery method according to claim 15 , wherein the step of performing sampling using the frequency divided clock signal to generate the second set of sample results comprises:
sampling the first set of sample results using the frequency divided clock signal to generate the second set of sample results.

17. The clock data recovery method according to claim 14 , wherein the step of performing sampling using the frequency divided clock signal to generate the second set of sample results comprises:
sampling the data signal using the frequency divided clock signal to generate the second set of sample results.

18. The clock data recovery method according to claim 14 , wherein the step of adjusting the original clock signal selectively according to one of the

Assignees

• Mstar Semiconductor Inc

Inventors

• Weng Meng-Tse
• Yeh Chun-Wen
• Lee Jiunn-Yih

Classifications

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04L7/0276

  Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title