Fractional-N PLL based clock recovery for SerDes

Patent metadata

Field	Value
Publication number	US-10313105-B2
Application number	US-201715702715-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Sep 12, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop, a phase interpolator, a sampling element, a phase detector, a phase control filter, and a frequency control filter. The phase interpolator applies a controllable phase shift to the clock signal from the frac-N PLL to provide a sampling signal to the sampling element. The phase detector estimates timing error of the sampling signal relative to the analog receive signal. The phase control filter derives a phase control signal for the phase interpolator which operates to minimize a phase component of the estimated timing error. The frequency control filter derives the frequency control signal in a fashion that separately minimizes a frequency offset component of the estimated timing error, reducing the interpolator's phase rotation rate.

First claim

What is claimed is:

1. An integrated receiver circuit that comprises:
a fractional-N phase lock loop that provides a clock signal based at least in part on a frequency control signal;
a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal;
a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal;
a phase detector that estimates timing error of the sampling signal relative to the analog receive signal;
a phase control filter that derives, from the estimated timing error, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase component of the estimated timing error; and
a frequency control filter that derives said frequency control signal from the estimated timing error, wherein the frequency control signal minimizes a frequency offset component of the estimated timing error.

2. The receiver circuit of claim 1 , further comprising a demodulator that extracts a transmitted symbol stream from the digital receive signal.

3. The receiver circuit of claim 2 , further comprising an interface module that receives the transmitted symbol stream and performs error correction.

4. The receiver circuit of claim 1 , wherein the phase detector derives the estimated timing error from the digital receive signal.

5. The receiver circuit of claim 1 , wherein the phase detector derives the estimated timing error by comparing the sampling signal to the analog receive signal.

6. The receiver circuit of claim 1 , wherein the fractional-N phase lock loop comprises:
a multi-modulus divider that converts the clock signal into a divided-frequency clock signal;
a phase-frequency detector that estimates phase error of the divided-frequency clock signal relative to a reference clock signal;
a loop filter that derives a filtered signal from the estimated phase error; and
a voltage-controlled oscillator that converts the filtered signal into said clock signal.

7. The receiver circuit of claim 6 , wherein the fractional-N phase lock loop further comprises a delta-sigma modulator that converts the frequency control signal into a modulus selector signal for the multi-modulus divider.

8. The receiver circuit of claim 1 , wherein the frequency control filter includes an integration element.

9. The receiver circuit of claim 8 , wherein the phase control filter includes an integration element.

10. The receiver circuit of claim 1 , wherein the analog receive signal represents a light signal intensity received via an optical fiber coupled to the receiver circuit.

11. A clock recovery method that comprises, in an integrated receiver circuit:
receiving an analog receive signal;
sampling the analog receive signal with a sampling element to obtain a digital receive signal, the sampling element sampling the analog receive signal in response to a sampling signal;
estimating timing error of the sampling signal relative to the analog receive signal using a phase detector;
filtering the estimated timing error with a phase control filter to provide a phase control signal;
filtering the estimated timing error with a frequency control filter to provide a frequency control signal;
using a fractional-N phase lock loop to generate a clock signal having a frequency controlled by the frequency control signal; and
producing said sampling signal with a phase interpolator that adjusts a phase of the clock signal based on the phase control signal.

12. The method of claim 11 , further comprising demodulating the digital receive signal to extract a transmitted symbol stream.

13. The method of claim 12 , further comprising performing error correction decoding of the transmitted symbol stream.

14. The method of claim 11 , wherein the phase detector derives the estimated timing error from the digital receive signal.

15. The method of claim 11 , wherein the phase detector derives the estimated timing error by comparing the sampling signal to the analog receive signal.

16. The method of claim 11 , wherein said generating the clock signal includes:
converting the clock signal into a divided-frequency clock signal with a multi-modulus divider;
estimating phase error of the divided-frequency clock signal relative to a reference clock signal using a phase-frequency detector;
deriving a filtered signal from the estimated phase error with a loop filter; and
converting the filtered signal into said clock signal using a voltage-controlled oscillator.

17. The method of claim 16 , wherein said generating the clock signal further includes using a delta-sigma modulator to convert the frequency control signal into a modulus selector signal for the multi-modulus divider.

18. The method of claim 11 , wherein the frequency control filter includes an integration element.

19. The method of claim 18 , wherein the phase control filter includes an integration element.

20. The method of claim 11 , wherein the analog receive signal represents a light signal intensity received via an optical fiber coupled to the integrated receiver circuit.

Assignees

• Credo Tech Group Ltd
• Credo Tech Group Ltd

Inventors

• Gao Xiang
• Qian Haoli

Classifications

• H04L27/148

  using filters, including PLL-type filters · CPC title

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title