III-V and Zn based finFET structure formed using low temperature deposition techniques

Patent metadata

Field	Value
Publication number	US-10777665-B2
Application number	US-201916543365-A
Country	US
Kind code	B2
Filing date	Aug 16, 2019
Priority date	Apr 20, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Aspects of the present disclosure include a semiconductor structure comprising a gate layer with an associated gate dielectric thereon, and a region comprising at least one fin structure in contact with the gate layer, wherein the fin structure includes at least two distinct materials, and wherein one of the two distinct materials is a Zn based material.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a gate layer with an associated gate dielectric; and
a region comprising at least one fin structure in contact with the gate dielectric, wherein the fin structure includes at least two distinct materials, and wherein one of the two distinct materials includes aluminum-doped zinc oxide (AZO) in a non-channel region of the fin structure.

2. The semiconductor structure according to claim 1 further comprising: a passivation layer at an interface between the two distinct materials of the fin structure.

3. The semiconductor structure according to claim 2 further, wherein the second distinct material of the fin structure comprises a Ill-V material.

4. The semiconductor structure according to claim 3 , wherein the second distinct material of the fin structure comprises InGaAs.

5. The semiconductor structure according to claim 4 , wherein the passivation layer comprises an Al based material.

6. The semiconductor structure according to claim 5 , wherein the passivation layer comprises Al2O3.

7. The semiconductor structure according to claim 6 further comprising: at least one nitride spacer material in contact with the gate layer and the fin structure.

8. A semiconductor structure comprising:
a gate structure comprising a gate dielectric in contact with a III-V fin structure; and
a spacer material in contact with the gate structure and the III-V fin structure, wherein the spacer material forms at least one sidewall spacer in contact with the gate, wherein a portion of the III-V fin structure creates an opening between at least two portions of the spacer material, and wherein the spacer material, the III-V fin structure, and the gate structure include a Zn based material.

9. The semiconductor structure of claim 8 , wherein the Zn based material forms a dual-material fin structure, wherein the dual material fin structure comprises a portion of the Zn based material and the III-V fin structure.

10. The semiconductor structure of claim 9 further comprising: a passivation layer at an interface of the III-V fin structure and the portion of Zn based material of the dual-material fin structure.

11. The semiconductor structure of claim 10 , wherein the passivation layer is an Al2O3 layer.

12. The semiconductor structure of claim 11 , wherein the Zn based material is included in an AZO doped layer.

13. The semiconductor structure of claim 12 , wherein the Zn based material is ZnO and the III-V fin structure comprises InGaAs.

14. A semiconductor structure comprising:
a gate in contact with a first set of sidewall spacers, wherein the first set of sidewall spacers covers opposite sides of a face of the gate;
a fin structure in contact with the gate and the first set of sidewall spacers, and in contact with a set of passivation layers, wherein the set of passivation layers covers opposite sides of a face of the fin structure;
a source in contact with a passivation layer from the set of passivation layers, and in contact with a second set of sidewall spacers, wherein the second set of sidewall spacers covers opposite sides of a face of the source and is in contact with a sidewall spacer from the first set of sidewall spacers; and
a drain in contact with a passivation layer from the set of passivation layers, and in contact with a third set of sidewall spacers, wherein the third set of sidewall spacers covers opposite sides of a face of the drain and is in contact with a sidewall spacer from the first set of sidewall spacers.

15. The structure according to claim 14 , wherein the fin structure comprises InGaAs.

16. The semiconductor structure according to claim 14 , wherein the set of passivation layers includes at least one passivation layer comprising an aluminum based material.

17. The semiconductor structure according to claim 16 , wherein the set of passivation layers includes at least one passivation layer comprising aluminum oxide (Al2O3).

18. The semiconductor structure according to claim 14 , wherein the source comprises aluminum-doped zinc oxide (AZO).

19. The structure according to claim 14 , wherein the drain comprises aluminum-doped zinc oxide (AZO).

Assignees

• IBM

Inventors

• Lee Yun Seog
• Sadana Devendra
• De Souza Joel P
• Wacaser Brent A

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P50/646

  of Group III-V materials · CPC title

• H10P14/6312

  of Group III-V semiconductors · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title