Economical and environmentally friendly chemical mechanical polishing for III-V compound semiconductor device fabrication

Patent metadata

Field	Value
Publication number	US-9601482-B1
Application number	US-201514962012-A
Country	US
Kind code	B1
Filing date	Dec 8, 2015
Priority date	Dec 8, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Compound semiconductor devices and methods for fabricating compound semiconductor devices (e.g., III-V devices) based on aspect ratio trapping are provided in which economical and environmentally friendly chemical mechanical polishing techniques are implemented to minimize waste of, e.g., III-V precursor material, minimize production costs, and minimize environmental impact from toxic waste generated from chemical mechanical polishing of III-V films.

First claim

We claim:

1. A method, comprising:
forming an insulating layer on a semiconductor substrate, wherein the insulating layer comprises a trench and an open region formed in the insulating layer down to the semiconductor substrate;
performing an epitaxial deposition process to deposit compound semiconductor material in the trench and in the open region of the insulating layer;
terminating the epitaxial deposition process at some point in the deposition process when the trench is over filled with the compound semiconductor material, thereby forming excess compound semiconductor material protruding from the trench, and the open region is partially filled with the compound semiconductor material;
depositing a layer of sacrificial material on the surface of the insulating layer to cover the excess compound semiconductor material protruding from the trench and to fill a remaining portion of the open region with the sacrificial material; and
performing a CMP (chemical mechanical polishing) process to form a planarized surface by removing the sacrificial material on the surface of the insulating layer and removing the excess compound semiconductor material protruding from the trench.

2. The method of claim 1 , wherein the CMP process is performed using a chemical slurry that etches the sacrificial material and the compound semiconductor material selective to the insulating layer.

3. The method of claim 1 , wherein the compound semiconductor material comprises a III-V compound semiconductor material, wherein the III-V compound material comprises As (arsenic).

4. The method of claim 1 , wherein the compound semiconductor material comprises a layer of GaAs (gallium arsenide) and a layer of InGaAs (Indium Gallium Arsenide).

5. The method of claim 1 , wherein the sacrificial material comprises an amorphous semiconductor material.

6. The method of claim 1 , wherein the sacrificial material comprises silicon germanium (SiGe) or germanium (Ge).

7. The method of claim 1 , wherein the sacrificial material comprises a dielectric material.

8. The method of claim 7 , wherein the dielectric material comprises silicon nitride.

9. The method of claim 1 , wherein the compound semiconductor material in the trench comprises a fin structure of a FinFET device, and wherein the compound semiconductor material in the open region comprises one of a passive device and an isolation structure.

10. A semiconductor device, comprising:
an insulating layer disposed on a semiconductor substrate, wherein the insulating layer comprises a trench and an open region formed in the insulating layer down to the semiconductor substrate;
wherein the trench is filled with III-V compound semiconductor material that forms a fin structure of an FET (field effect transistor) device;
wherein one end of the fin structure contacts the semiconductor substrate and wherein another end of the fin structure extends past a surface of the insulating layer to provide an active fin component of the FET device formed on the surface of the insulating layer;
wherein a bottom portion of the open region is filled with III-V compound semiconductor material, in contact with the semiconductor substrate, wherein an upper portion of the open region is filled with as sacrificial material which comprises a non-III-V semiconductor material; and
wherein the III-V compound semiconductor materials in the trench and the open region of the insulating layer are the same.

11. The semiconductor device of claim 10 , wherein the III-V compound semiconductor material in the open region composes one of a passive device and an isolation structure.

12. The semiconductor device of claim 10 , wherein the sacrificial material filling the upper portion of the open region in the insulating layer comprises an amorphous semiconductor material.

13. The semiconductor device of claim 10 , wherein the sacrificial material filling the upper portion of the open region in the insulating layer comprises a dielectric material.

14. The semiconductor device of claim 13 , wherein the dielectric material comprises silicon nitride.

15. The semiconductor device of claim 10 , wherein the sacrificial material filling the upper portion of the open region in the insulating layer comprises silicon germanium (SiGe) or germanium (Ge).

16. The semiconductor device of claim 10 , wherein the III-V compound semiconductor material that forms the fin structure comprises As (arsenic).

17. The semiconductor device of claim 10 , wherein the III-V compound semiconductor material that fills the trench comprises:
a first layer of III-V compound semiconductor material formed on the semiconductor substrate;
a second layer of III-V compound semiconductor material formed on the first layer of III-V compound semiconductor material; and
a third layer of III-V compound semiconductor material formed on the second layer of III-V compound semiconductor material.

18. The semiconductor device of claim 17 , wherein the first layer of III-V compound semiconductor material comprises GaAs (Gallium Arsenide), wherein the second layer of III-V compound semiconductor material comprises InP (Indium Phosphide), and wherein the third layer of III-V compound semiconductor material comprises InGaAs (Indium Gallium Arsenide).

19. The semiconductor device of claim 17 , wherein the first layer of III-V compound semiconductor material comprises GaAs (Gallium Arsenide), wherein the second layer of III-V compound semiconductor material comprises a first composition of InGaAs (Indium Gallium Arsenide), and wherein the third layer of III-V compound semiconductor material comprises a second composition of InGaAs, which is different from the first composition of InGaAs.

20. The semiconductor device of claim 17 , wherein the first and second layers of III-V compound semiconductor material comprise a graded buffer structure that serves to match a lattice constant of material of the semiconductor substrate to a lattice constant of the third layer of III-V compound semiconductor material.

Assignees

• IBM

Inventors

• Fogel Keith E
• Reznicek Alexander
• Sadana Devendra K
• Surisetty Charan V

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H01L21/823431

  Electricity · mapped topic

• H01L21/762

  Electricity · mapped topic