Executing load-store operations without address translation hardware per load-store unit port

Patent metadata

Field	Value
Publication number	US-10776113-B2
Application number	US-201916448383-A
Country	US
Kind code	B2
Filing date	Jun 21, 2019
Priority date	Oct 6, 2017
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Technical solutions are described for out-of-order (OoO) execution of one or more instructions by a processing unit includes receiving, by a load-store unit (LSU) of the processing unit, an OoO window of instructions including a plurality of instructions to be executed OoO, and issuing, by the LSU, instructions from the OoO window. The issuing includes selecting an instruction from the OoO window, the instruction using an effective address. Further, in response to the instruction being a load instruction, it is determined whether the effective address is present in an effective address directory (EAD). In response to the effective address being present in the EAD, the load instruction is issued using the effective address. Further, in response to the instruction being a store instruction, a real address mapped to the effective address is determined from an effective-real translation (ERT) table, and the store instruction is issued using the real address.

First claim

What is claimed is:

1. A computer-implemented method for out-of-order execution of one or more instructions by a processing unit, the method comprising:
receiving, by a load-store unit (LSU) of the processing unit, an out-of-order (OoO) window of instructions comprising a plurality of instructions to be executed OoO; and
issuing, by the LSU, instructions from the OoO window, the issuing comprising:
selecting an instruction from the OoO window, the instruction using an effective address;
in response to the instruction being a load instruction:
determining whether the effective address is present in an effective address directory (EAD), wherein the EAD comprises a plurality of EAD entries, an EAD entry mapping the effective address with a corresponding effective-real translation (ERT) entry using an ERT index; and
in response to the effective address being present in the EAD, issuing the load instruction using the effective address; and
in response to the instruction being a store instruction:
determining a real address of the store instruction mapped to the effective address from the ERT table; and
issuing the store instruction using the real address.

2. The computer-implemented method of claim 1 , wherein issuing the load instruction comprises creating an entry for the load instruction in a load reorder queue, wherein the entries in the load reorder queue are executed out of order.

3. The computer-implemented method of claim 1 , wherein issuing the store instruction comprises creating an entry for the store instruction in a store reorder queue, wherein the entries in the store reorder queue are executed in sequential order.

4. The computer-implemented method of claim 1 , wherein executing the plurality of instructions in the OoO window further comprises:
detecting a hazard based on the effective address without translation to real address, wherein the hazard includes one from a group of hazards consisting of a load-hit-load hazard, a store-hit-load hazard, and a load-hit-store hazard.

5. The computer-implemented method of claim 1 , wherein the corresponding ERT entry comprises the ERT index, the effective address, a corresponding real address, and a thread identifier.

6. A processing unit for executing one or more instructions, the processing unit comprising:
a load-store unit (LSU) for transferring data between memory and registers, the LSU configured to execute a plurality of instructions in an out-of-order (OoO) window by:
selecting an instruction from the OoO window, the instruction using an effective address;
in response to the instruction being a load instruction:
determining whether the effective address is present in an effective address directory (EAD), wherein the EAD comprises a plurality of EAD entries, an EAD entry mapping the effective address with a corresponding effective-real translation (ERT) entry using an ERT index; and

in response to the effective address being present in the EAD, issuing the load instruction using the effective address; and

in response to the instruction being a store instruction:
determining a real address of the store instruction mapped to the effective address from the ERT table; and
issuing the store instruction using the real address.

7. The processing unit of claim 6 , wherein issuing the load instruction comprises creating an entry for the load instruction in a load reorder queue, wherein the entries in the load reorder queue are executed out of order.

8. The processing unit of claim 6 , wherein issuing the store instruction comprises creating an entry for the store instruction in a store reorder queue, wherein the entries in the store reorder queue are executed in sequential order.

9. The processing unit of claim 6 , wherein executing the plurality of instructions in the OoO window further comprises:
detecting a hazard based on the effective address without translation to real address, wherein the hazard includes one from a group of hazards consisting of a load-hit-load hazard, a store-hit-load hazard, and a load-hit-store hazard.

10. The processing unit of claim 6 , wherein the corresponding ERT entry comprises the ERT index, the effective address, a corresponding real address, and a thread identifier.

11. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
receiving, by a load-store unit (LSU) of the processing unit, an out-of-order window of instructions comprising a plurality of instructions to be executed out-of-order; and
issuing, by the LSU, instructions from the OoO window, the issuing comprising:
selecting an instruction from the OoO window, the instruction using an effective address;
in response to the instruction being a load instruction:
determining whether the effective address is present in an effective address directory (EAD), wherein the EAD comprises a plurality of EAD entries, an EAD entry mapping the effective address with a corresponding effective-real translation (ERT) entry using an ERT index; and
in response to the effective address being present in the EAD, issuing the load instruction using the effective address; and

in response to the instruction being a store instruction:
determining a real address of the store instruction mapped to the effective address from the ERT table; and

issuing the store instruction using the real address.

12. The computer program product of claim 11 , wherein issuing the load instruction comprises creating an entry for the load instruction in a load reorder queue, wherein the entries in the load reorder queue are executed out of order.

13. The computer program product of claim 11 , wherein issuing the store instruction comprises creating an entry for the store instruction in a store reorder queue, wherein the entries in the store reorder queue are executed in sequential order.

14. The computer program product of claim 11 , wherein executing the plurality of instructions in the OoO window further comprises:
detecting a hazard based on the effective address without translation to real address, wherein the hazard includes one from a group of hazards consisting of a load-hit-load hazard, a store-hit-load hazard, and a load-hit-store hazard.

15. The computer program product of claim 11 , wherein the corresponding ERT entry comprises the ERT index, the effective address, a corresponding real address, and a thread identifier.

Assignees

• IBM

Inventors

• Gonzalez Christopher
• Lloyd Bryan
• Sinharoy Balaram

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title