Source/drain contacts for non-planar transistors

Patent metadata

Field	Value
Publication number	US-10770591-B2
Application number	US-201916360309-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Oct 1, 2011
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

First claim

What is claimed is:

1. A microelectronic device, comprising:
a substrate;
a transistor on the substrate comprising a pair of gate spacers, a gate dielectric layer between the pair of gate spacers and adjacent the substrate, a gate electrode between the pair of gate spacers and adjacent the gate dielectric, and a capping dielectric layer between the pair of gate spacer and adjacent the gate electrode;
a dielectric material on the substrate and the transistor;
a source region in the substrate;
a drain region in the substrate;
a source contact extending through the dielectric material, wherein the source contact is adjacent the source region;
a drain contact extending through the dielectric material, wherein the drain contact is adjacent the drain region;
wherein at least one of the source contact and the drain contact comprises an interface adjacent its respective source region or drain region, a contact interface layer adjacent the interface, and a conductive contact material adjacent the contact interface layer; and
wherein the contact interface layer abuts at least one of a portion of one gate spacer and at least a portion of the capping structure.

2. The microelectronic device of claim 1 , wherein the substrate comprises silicon.

3. The microelectronic device of claim 1 , wherein the conductive contact material comprises tungsten.

4. The microelectronic device of claim 1 , wherein the contact interface layer comprises titanium.

5. The microelectronic device of claim 4 , wherein the contact interface layer comprises substantially pure titanium.

6. The microelectronic device of claim 1 , wherein the interface comprises titanium and silicon.

7. The microelectronic device of claim 1 , wherein the contact interface layer abuts at least the portion of one gate spacer and at least the portion of the capping structure.

8. The microelectronic device of claim 1 , wherein the interface resides substantially only between the contact interface layer and the at least one of the source region and the drain region.

9. The microelectronic device of claim 1 , wherein the substrate comprises a fin structure.

10. A method of fabricating a microelectronic device, comprising:
forming a substrate;
forming a transistor on the substrate comprising:
forming a pair of gate spacers, forming a gate dielectric layer between the pair of gate spacers and adjacent the substrate;
forming a gate electrode between the pair of gate spacers and adjacent the gate dielectric; and
forming a capping dielectric layer between the pair of gate spacer and adjacent the gate electrode;

forming a source region in the substrate;
forming a drain region in the substrate;
forming a dielectric material on the substrate and the transistor;
forming a contact opening through the dielectric material to expose a portion of one of the source region and the drain region;
forming an interface adjacent the portion of one of the source region and the drain region;
forming contact interface layer adjacent the interface, wherein the contact interface layer abuts at least one of a portion of one gate spacer and at least a portion of the capping structure; and
forming a conductive contact material adjacent the contact interface layer.

11. The method of claim 10 , wherein forming the substrate comprises forming a substrate comprising silicon.

12. The method of claim 10 , wherein forming the conductive contact material comprises forming a conductive contact material comprising tungsten.

13. The method of claim 10 , wherein forming the contact interface layer comprises depositing a conformal a contact interface layer.

14. The method of claim 10 , wherein forming the contact interface layer comprises forming a contact interface layer comprising titanium.

15. The method of claim 14 , wherein forming the contact interface layer comprises forming a substantially pure titanium contact interface layer.

16. The method of claim 10 , wherein forming the interface comprises titanium and silicon.

17. The method of claim 16 , wherein forming the interface comprises:
forming the substrate comprising silicon;
forming the contact interface layer comprising titanium, and
heating the substrate and the contact interface layer.

18. The method of claim 10 , wherein forming the interface comprises forming the interface to reside substantially only between the contact interface layer and the at least one of the source region and the drain region.

19. The method of claim 10 , wherein forming the contact interface layer comprises forming the contact interface layer to abut at least the portion of one gate spacer and at least the portion of the capping structure.

20. The method of claim 10 , wherein forming the substrate comprises forming a fin structure.

Assignees

• Intel Corp

Inventors

• Pradhan Sameer S
• Joshi Subhash M
• Chun Jin-Sung

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/414

  of metal-silicide materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title