Micro-LED display assembly

Patent metadata

Field	Value
Publication number	US-10770440-B2
Application number	US-201715459336-A
Country	US
Kind code	B2
Filing date	Mar 15, 2017
Priority date	Mar 15, 2017
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.

First claim

What is claimed:

1. A structure, comprising:
an interposer;
a plurality of light emitting diode (LED) arrays each of which comprise a plurality of pixels composed of multiple sub-pixels;
a plurality of through-vias composed of an insulator liner, diffusion barrier metal and electroplated metallization feature, each through via of the plurality of through-vias being directly below and connecting to each pixel of the plurality of pixels of each of the plurality of LED arrays by a metal pad that is in physical contact and directly below the each pixel, wherein each through via of the plurality of through vias is further connected to the interposer and a single through via is used per pixel; and
a horizontal plate composed of GaN, wherein the plurality of pixels share the horizontal plate composed of GaN from above the plurality of pixels.

2. The structure of claim 1 , wherein the interposer is a silicon interposer with driver circuits.

3. The structure of claim 1 , wherein the interposer is a glass interposer.

4. The structure of claim 1 , wherein the through-vias are through silicon vias.

5. The structure of claim 4 , wherein each of the pixels is connected to the interposer by a separate one of the through silicon vias.

6. The structure of claim 1 , wherein the pixels are composed of GaN and the through-vias are copper through silicon vias integrated into a same die as the pixels.

7. The structure of claim 1 , wherein the through-vias are connected to the interposer by pillars which match a pitch of the through-vias.

8. The structure of claim 1 , wherein the plurality of LED arrays are equally spaced apart on the interposer.

9. The structure of claim 8 , wherein an across die pixel pitch is equal to a pixel pitch within each of the plurality of LED arrays.

10. The structure of claim 1 , wherein a diameter of the through vias is about ½ a pixel pitch.

11. The structure of claim 1 , further comprising a back-end of the line wiring scheme which is interposed between the interposer and the plurality of LED arrays, the back-end of the line wiring scheme connects the each of the plurality of through-vias of each of the pixels to the interposer by separate pillars aligned with each of the plurality of through-vias of each of the pixels.

12. A structure comprising:
an interposer comprising a plurality of through vias;
a plurality of light emitting diode (LED) arrays each of which comprises a plurality of pixels, a plurality of through-vias composed of an insulator liner, a barrier metal and electroplated metallization feature and each one of the plurality of through vias being directly below and connecting a separate pixel of the plurality of pixels by a metal pad that is directly below and in physical contact with the separate pixel, and wherein each pixel of the plurality of pixels is composed of multiple sub-pixels;
a back-end of the line wiring scheme which is positioned between and connected to the interposer and the plurality of LED arrays by a plurality of pillars, wherein each pillar of the plurality of pillars is aligned with and connects to the separate pixel of the plurality of pixels by a respective one of the plurality of through-vias such that only a single pillar the single pixel, respectively; and
a horizontal plate composed of GaN, wherein the plurality of pixels share the horizontal plate composed of GaN from above the plurality of pixels.

13. The structure of claim 12 , wherein:
the plurality of LED arrays are equally spaced apart; and
an across die pixel pitch is equal to a pixel pitch within each of the plurality of -LED arrays.

14. The structure of claim 13 , wherein the pixels are composed of GaN and the through-vias of the plurality of the plurality of LED arrays are copper through silicon vias integrated into a same die as the pixels.

15. The structure of claim 14 , wherein the through silicon vias are connected to the back end of the-line wiring scheme by the pillars.

16. The structure of claim 15 , wherein the pillars are solder connections.

17. The structure of claim 15 , wherein the pillars match a pitch of the through silicon vias.

18. The structure of claim 14 , wherein a diameter of each through-via is about ½ a pixel pitch.

19. The structure of claim 12 , wherein the back-end of the line interposer is a silicon interposer with driver circuits.

20. The structure of claim 12 , wherein the back-end of the line interposer is a glass interposer.

Assignees

• Globalfoundries Inc

Inventors

• England Luke
• Pawlak Bartlomiej Jan

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/825

  containing nitrogen, e.g. GaN · CPC title