Wafer level packaging of multiple light emitting diodes (LEDs) on a single carrier die

Patent metadata

Field	Value
Publication number	US-9666764-B2
Application number	US-201313801743-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Apr 9, 2012
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide multiple LED dies that are joined to a single carrier die. The multiple LED dies on the single carrier die are connected in series and/or in parallel by interconnection in the LED dies and/or in the single carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. Related devices and fabrication methods are described.

First claim

What is claimed is:

1. A Light Emitting Diode (LED) chip, comprising:
an LED substrate including a plurality of LED dies, a respective LED die including an anode and a cathode;
a patterned internal interconnection layer that is internal to the plurality of LED dies and that is configured to selectively electrically connect the anodes and cathodes of the plurality of LED dies in series and/or in parallel internal to the plurality of LED dies;
an LED die anode contact that is electrically connected to at least one of the anodes; and
an LED die cathode contact that is electrically connected to at least one of the cathodes,
wherein the patterned internal interconnection layer that is internal to the plurality of LED dies includes a first patterned internal interconnection layer face and a second patterned internal interconnection layer face that is opposite the first patterned internal interconnection layer face,
wherein each of the plurality of LED dies includes a first layer that is on the first patterned internal interconnection layer face opposite the second patterned internal interconnection layer face, and a second layer that is on the second patterned internal interconnection layer face opposite the first patterned internal interconnection layer face,
wherein the LED die anode contact penetrates through the first and second layers, penetrates through the first patterned internal interconnection layer face, penetrates through the second patterned internal interconnection layer face, electrically connects to the patterned internal interconnection layer and electrically connects to the at least one of the anodes, and
wherein the LED die cathode contact penetrates through the first and second layers, penetrates through the first patterned internal interconnection layer face, penetrates through the second patterned internal interconnection layer face, electrically connects to the patterned internal interconnection layer and electrically connects to the at least one of the cathodes.

2. The LED chip according to claim 1 wherein the first and second layers comprise first and second insulating layers, respectively, and the patterned internal interconnection layer comprises a patterned internal metal layer.

3. The LED chip according to claim 1 further comprising:
a carrier die having first and second opposing faces, the carrier die having a first anode contact and a first cathode contact on the first face and a second anode contact and a second cathode contact on the second face, the carrier die being joined to the LED substrate so that the plurality of LED dies are adjacent the first face, the first anode contact is electrically connected to the LED die anode contact and the first cathode contact is electrically connected to the LED die cathode contact.

4. The LED chip according to claim 3 wherein the LED substrate includes beveled sidewalls between adjacent LED dies.

5. The LED chip according to claim 4 wherein the LED substrate includes a beveled edge at a periphery thereof.

6. The LED chip according to claim 4 further comprising a wavelength conversion material layer on the LED substrate remote from the carrier die, and extending onto the beveled sidewalls between adjacent LED dies, the wavelength conversion material layer including opposing surfaces that both conform to the beveled sidewalls between adjacent LED dies.

7. The LED chip according to claim 5 further comprising a wavelength conversion material layer on the LED substrate remote from the carrier die, and extending onto the beveled sidewalls between adjacent LED dies and onto the beveled edge at the periphery of the LED substrate, the wavelength conversion material layer including opposing surfaces that both conform to the beveled sidewalls between adjacent LED dies and to the beveled edge at the periphery of the LED substrate.

8. The LED chip according to claim 7 wherein the wavelength conversion material layer further extends onto a sidewall of the LED die at the periphery of the LED substrate.

9. The LED chip according to claim 3 further comprising:
a mounting substrate on the second face of the carrier die and electrically connected to the second anode contact and the second cathode contact.

10. The LED chip according to claim 3 in combination with:
a light fixture housing in which the carrier die is mounted to provide a light fixture.

11. The LED chip according to claim 3 wherein the carrier die further comprises at least one thermal contact on the first and/or second face.

12. The LED chip according to claim 3 wherein the carrier die comprises silicon.

13. The LED chip according to claim 3 wherein the carrier die comprises an internal reflector between the first and second faces thereof.

14. The LED chip according to claim 1 wherein the patterned internal interconnection layer comprises:
a crack reducing layer that is configured to reduce propagation of cracks between the first and second layers; and
a crack reducing layer extension that extends from the crack reducing layer to selectively electrically connect the anodes and cathodes of the plurality of LED dies in series and/or in parallel internal to the plurality of LED dies.

15. A Light Emitting Diode (LED) chip, comprising:
a plurality of LED dies in a common substrate, a respective one of which includes an anode contact and a cathode contact on a face thereof;
a carrier die having first and second opposing faces, a plurality of internal contacts on the first face and an external anode contact and an external cathode contact on the second face, wherein the plurality of LED dies in the common substrate includes a patterned internal interconnection layer that is internal to the plurality of LED dies and that is configured to electrically connect the anode and cathode contacts of the plurality of LED dies in series and/or in parallel internal to the plurality of LED dies;
the plurality of LED dies and the carrier die being joined to one another so that the anode and cathode contacts of the LED dies are adjacent the first face of the carrier die and the anode and cathode contacts of the plurality of LED dies are connected in series and/or in parallel,
wherein the patterned internal interconnection layer that is internal to the plurality of LED dies includes a first patterned internal interconnection layer face and a second patterned internal interconnection layer face that is opposite the first patterned internal interconnection layer face,
wherein each of the plurality of LED dies includes a first layer that is on the first patterned internal interconnection layer face opposite the second patterned internal interconnection layer face, and a second layer that is on the second patterned internal interconnection layer face opposite the first patterned internal interconnection layer face,
wherein the anode contact penetrates through the first and second layers, penetrates through the first patterned internal interconnection layer face, penetrates through the second patterned internal interconnection layer face and electrically connects to the patterned internal interconnection layer, and
wherein the cathode contact penetrates through the first and second layers, penetrates through the first patterned internal interconnection layer face, penetrates through the second patterned internal interconnection layer face and electrically connects to the patterned internal interconnection layer.

16. The LED chip according to claim 15 wherein the patterned internal interconnection layer comprises:
a crack reducing layer that is configured to reduce propagation of crac

Assignees

• Cree Inc

Inventors

• Bergmann Michael John
• Haberern Kevin
• Dillon Alan Wellford

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W80/314

  characterized by direct bonding of pads or other interconnections · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07232

  Compression bonding, e.g. thermocompression bonding · CPC title

• H10W72/072

  of bump connectors · CPC title