Semiconductor structure

Patent metadata

Field	Value
Publication number	US-10763229-B2
Application number	US-201916679051-A
Country	US
Kind code	B2
Filing date	Nov 8, 2019
Priority date	Oct 30, 2015
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A semiconductor structure includes a transceiver, a molding surrounding the transceiver, a plurality of vias extending through the molding, and a RDL disposed over the transceiver and the plurality of vias. In some embodiments, the RDL includes an antenna disposed over and electrically connected to the transceiver, and a dielectric layer surrounding the antenna. In some embodiments, the antenna includes an elongated portion extending over the molding and a via portion electrically connected to the transceiver.

First claim

The invention claimed is:

1. A semiconductor structure, comprising:
a transceiver;
a molding surrounding the transceiver;
a plurality of vias extending through the molding; and
a redistribution layer (RDL) disposed over the transceiver and the plurality of vias, wherein the RDL comprises:
an antenna disposed over and electrically connected to the transceiver; and
a dielectric layer surrounding the antenna,

wherein the antenna comprises an elongated portion extending over the molding and a via portion electrically connected to the transceiver.

2. The semiconductor structure of claim 1 , further comprising a pillar disposed between the antenna and the transceiver, wherein the pillar is surrounded by the molding.

3. The semiconductor structure of claim 2 , wherein a height of the plurality of vias is greater than a height of the pillar.

4. The semiconductor structure of claim 2 , further comprising an insulating layer disposed over the molding, the plurality of vias and the pillar.

5. The semiconductor structure of claim 4 , wherein the via portion of the antenna extends through the insulating layer to contact the pillar and electrically connect to the transceiver through the pillar.

6. The semiconductor structure of claim 1 , wherein each of the plurality of vias is a through integrated circuit via (TIV) extending through the molding and inductively coupled with the antenna.

7. A semiconductor structure, comprising:
a transceiver;
a molding surrounding the transceiver;
a plurality of vias extending through the molding;
a redistribution layer (RDL) disposed over the transceiver and the plurality of vias, wherein the RDL comprises:
an antenna disposed over and electrically connected to the transceiver; and
a dielectric layer surrounding the antenna; and

a pillar disposed between the antenna and the transceiver and surrounded by the molding, wherein the pillar electrically connects the antenna to the transceiver, wherein the antenna comprises an elongated portion extending over the molding and a via portion electrically connected to the pillar.

8. The semiconductor structure of claim 7 , wherein the antenna is configured to receive a signal in a predetermined electromagnetic frequency from a transmitter, and the plurality of vias is configured to receive the charging power from the transmitter.

9. The semiconductor structure of claim 8 , wherein each of the plurality of vias is a through integrated circuit via (TIV) extending through the molding and inductively coupled with the antenna.

10. The semiconductor structure of claim 7 , wherein the antenna has a resonance frequency of about 2.4 GHz.

11. The semiconductor structure of claim 7 , further comprising an insulating layer disposed over the molding, the plurality of vias and the pillar.

12. The semiconductor structure of claim 11 , wherein the via portion of the antenna extends through the insulating layer to contact the pillar.

13. The semiconductor structure of claim 7 , wherein the pillar and the antenna comprise a same material.

14. The semiconductor structure of claim 7 , wherein a height of the plurality of vias is greater than a height of the pillar.

15. A semiconductor structure comprising:
a transceiver;
a molding surrounding the transceiver;
a plurality of vias extending through the molding;
an insulating layer disposed over the molding, the transceiver and the plurality of vias;
a redistribution layer (RDL) disposed over the insulating layer, wherein the RDL comprises:
an antenna disposed over and electrically connected to the transceiver; and
a first interconnect structure electrically connected to the plurality of vias; and

a pillar disposed between the antenna and the transceiver and surrounded by the molding, wherein the pillar electrically connects the antenna to the transceiver, wherein a portion of the antenna extends through the insulating layer to electrically connect to the pillar.

16. The semiconductor structure of claim 15 , wherein each of the plurality of vias is a through integrated circuit via (TIV) extending through the molding and inductively coupled with the antenna.

17. The semiconductor structure of claim 15 , wherein a height of the plurality of vias is greater than a height of the pillar.

18. The semiconductor structure of claim 15 , further comprising a charger and a resonator separated from each other.

19. The semiconductor structure of claim 18 , wherein the RDL further comprises a second interconnect structure electrically connected to the charger.

20. The semiconductor structure of claim 18 , wherein the antenna overlaps a portion of the transceiver and entirely offset from the charger and the resonator.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Vincent
• Kuo Hung-Yi
• Wang Chuei-Tang
• Tsai Hao-Yi
• Yu Chen-Hua
• Chen Wei-Ting
• Tseng Ming Hung
• Lin Yen-Liang

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title