Method for forming a multi-level interconnect structure

Patent metadata

Field	Value
Publication number	US-10763159-B2
Application number	US-201916518361-A
Country	US
Kind code	B2
Filing date	Jul 22, 2019
Priority date	Jul 23, 2018
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.

First claim

What is claimed is:

1. A method for forming a multi-level interconnect structure on a substrate, comprising:
forming on a substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer; thereafter
forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer; and thereafter
forming on the second interconnection level a third interconnection level, wherein forming the third interconnection level comprises:
forming a third dielectric layer,
forming a trench mask on the third dielectric layer, the trench mask comprising a pattern of trenches for defining positions of a third set of conductive structures to be formed in the third dielectric layer,
forming a multi-level via hole by etching the third dielectric layer in a region exposed within one of the trenches, the multi-level via hole extending through the third dielectric layer and the second dielectric layer to a structure of the first set of conductive structures such that a surface of the structure is exposed at a bottom of the multi-level via hole,
selectively depositing a first conductive material in the multi-level via hole on the structure of the first set of conductive structures,
transferring the pattern of the trench mask into the third dielectric layer by etching to form a set of dielectric layer trenches for accommodating the third set of conductive structures, and
depositing a second conductive material filling the set of dielectric layer trenches, wherein the second conductive material deposited in one of the dielectric layer trenches is deposited on the first conductive material selectively deposited in the multi-level via hole.

2. The method of claim 1 , wherein the dielectric layer trenches are formed with a depth in the third dielectric layer such that an upper surface of the first conductive material deposited in the multi-level via hole is exposed in the one trench of the set of trenches in the third dielectric layer.

3. The method of claim 1 , further comprising forming a dielectric liner covering a sidewall of the multi-level via hole and exposing the surface of the structure of the first set of conductive structures.

4. The method of claim 3 , wherein the dielectric liner is formed to further cover sidewalls of the trenches of the trench mask.

5. The method of claim 1 , wherein the first conductive material is selectively deposited in the multi-level via hole by an electro-less deposition process or an atomic layer deposition process.

6. The method of claim 1 , wherein the trench mask comprises a hard mask material.

7. A method for forming a multi-level interconnect structure on a substrate, comprising:
forming on a substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer;
forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer; and
forming on the second interconnection level a third interconnection level, wherein forming the third interconnection level comprises:
forming a third dielectric layer,
forming a trench mask on the third dielectric layer, the trench mask comprising a pattern of trenches for defining positions of a third set of conductive structures to be formed in the third dielectric layer,
forming a multi-level via hole by etching the third dielectric layer in a region exposed within one of the trenches, the multi-level via hole extending through the third dielectric layer and the second dielectric layer to a structure of the first set of conductive structures such that a surface of the structure is exposed at a bottom of the multi-level via hole,
selectively depositing a first conductive material in the multi-level via hole on the structure of the first set of conductive structures, wherein the first conductive material is selectively deposited to only partially fill the multi-level via hole,
transferring the pattern of the trench mask into the third dielectric layer by etching to form a set of dielectric layer trenches for accommodating the third set of conductive structures, and
depositing a second conductive material filling the set of dielectric layer trenches, wherein the second conductive material deposited in one of the dielectric layer trenches is deposited on the first conductive material selectively deposited in the multi-level via hole.

8. A method for forming a multi-level interconnect structure on a substrate, comprising:
forming on a substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer;
forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer; and
forming on the second interconnection level a third interconnection level, wherein forming the third interconnection level comprises:
forming a third dielectric layer,
forming a trench mask on the third dielectric layer, the trench mask comprising a pattern of trenches for defining positions of a third set of conductive structures to be formed in the third dielectric layer,
forming a via mask above the trench mask, the via mask including an opening exposing a region of the third dielectric layer,
forming a multi-level via hole by etching the third dielectric layer in the region exposed within one of the trenches, the multi-level via hole extending through the third dielectric layer and the second dielectric layer to a structure of the first set of conductive structures such that a surface of the structure is exposed at a bottom of the multi-level via hole, wherein the multi-level via hole is formed by transferring the opening into the third and second dielectric layers by etching,
selectively depositing a first conductive material in the multi-level via hole on the structure of the first set of conductive structures,
transferring the pattern of the trench mask into the third dielectric layer by etching to form a set of dielectric layer trenches for accommodating the third set of conductive structures, and
depositing a second conductive material filling the set of dielectric layer trenches, wherein the second conductive material deposited in one of the dielectric layer trenches is deposited on the first conductive material selectively deposited in the multi-level via hole.

9. A method for forming a multi-level interconnect structure on a substrate, comprising:
forming on a substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer;
forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer; and
forming on the second interconnection level a third interconnection level, wherein forming the third interconnection level comprises:
forming a third dielectric layer,
forming a trench mask on the third dielectric layer, the trench mask comprising a pattern of trenches for defining positions of a third set of conductive structures to be formed in the third dielectric layer,
forming a multi-level via hole by etching the third dielectric layer in a region exposed within one of the trenches, the multi-level via hole extending through the third dielectric layer a

Assignees

• Imec Vzw

Inventors

• Briggs Basoene
• Wilson Christopher
• Boemmels Juergen

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title