Method of forming an interconnect structure for a semiconductor device

Patent metadata

Field	Value
Publication number	US-9997404-B2
Application number	US-201615249805-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Oct 1, 2014
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A spacer material layer is formed over the plurality of trenches. A via pattern including a plurality of openings is formed over the spacer material layer and plurality of trenches. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.

First claim

What is claimed is:

1. A method of semiconductor fabrication, comprising:
providing a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate;
forming a spacer material layer on sidewalls, top surface, and bottom of each of the plurality of trenches;
defining a via pattern in a layer disposed above the plurality of trenches and spacer material layer disposed on the sidewalls, top surface and bottom of each of the plurality of trenches;
etching the spacer material layer from a bottom of a first trench of the plurality of trenches using the via pattern in the layer as a masking element during the etching the spacer material layer; and
etching a via hole in the dielectric layer using the etched spacer material layer as a masking element.

2. The method of claim 1 , further comprising:
removing the layer having the via pattern defined after etching the spacer material layer.

3. The method of claim 2 , further comprising:
forming another layer having another via pattern after etching the spacer material layer.

4. The method of claim 3 , further comprising:
performing a second etching of the spacer material layer using the another via pattern.

5. The method of claim 1 , wherein the etching the spacer material layer includes maintaining the spacer material layer on a bottom of at least one other trench of the plurality of trenches.

6. The method of claim 1 , further comprising:
filling the via hole with a conductive material.

7. The method of claim 1 , wherein the forming the spacer material layer includes forming a conformal layer of dielectric material, wherein the conformal layer is not etched prior to forming the via pattern.

8. A method, comprising:
forming a dielectric layer over a semiconductor substrate;
etching a plurality of trenches in the dielectric layer, wherein the plurality of trenches define a routing for a plurality of interconnect lines;
depositing a spacer material layer over the semiconductor substrate lining the plurality of trenches;
after depositing the spacer material layer, depositing a patterning layer over the plurality of trenches and spacer material layer;
defining a first opening in the patterning layer, wherein the first opening exposes a first trench of the plurality of trenches while the patterning layer is overlying a second trench of the plurality of trenches; and
etching a first portion of the spacer material layer from a bottom surface of the first trench through the first opening, while using the patterning layer as a masking element to maintain a second portion of the spacer material layer on a bottom surface of the second trench during the etching.

9. The method of claim 8 , wherein the depositing the spacer material layer is performed by an atomic layer deposition (ALD) process.

10. The method of claim 8 , wherein the depositing the spacer material layer is performed to a first thickness, and the patterning layer is formed over the spacer material layer having the first thickness on the bottom surface of the first and second trenches.

11. The method of claim 8 , further comprising:
removing the patterning layer and forming another patterning layer;
defining a second opening in the another patterning layer, wherein the second opening exposes a second trench of the plurality of trenches; and
etching a second portion of the spacer material layer from a bottom surface of the second trench simultaneously with etching the first portion.

12. The method of claim 8 , further comprising:
etching a via hole in the dielectric layer in a region defined by the etched first portion of the spacer material layer.

13. The method of claim 12 , further comprising:
forming a first hard mask layer and a second hard mask layer over the dielectric layer, wherein the plurality of trenches extend through the first and second hard mask layers.

14. The method of claim 8 , further comprising:
etching a via hole in the dielectric layer in a region defined by the etched first portion of the spacer material layer, wherein the etching the via hole creates a via connected to and underlying the first trench.

15. The method of claim 14 , further comprising:
using a deposition process, providing a conductive material in the first trench and the via.

16. A method of semiconductor fabrication, comprising:
providing a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate;
forming a conformal layer over the plurality of trenches, wherein the conformal layer includes one of titanium oxide and titanium nitride;
define a via pattern in a patterning layer disposed above the plurality of trenches and conformal layer;
etching the conformal layer using the via pattern in the patterning layer; and
thereafter, etching the dielectric layer using the etched conformal layer as a masking element.

17. The method of claim 16 , wherein the conformal layer is deposited using atomic layer deposition.

18. The method of claim 16 , further comprising:
after the etching the dielectric layer, removing the etched conformal layer from the substrate.

19. The method of claim 18 , wherein the removing is performed by a hydrogen peroxide (H 2 O 2 ) etch.

20. The method of claim 16 , wherein during the etching the dielectric layer the etched conformal layer is disposed on sidewalls of each of the plurality of trenches.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Yung-Hsu
• Tsai Cheng-Hsiung
• Chang Yu-Sheng
• Wu Chia-Tien
• Lee Chung-Ju
• Yen Yung-Sung
• Chen Chun-Kuang
• Bao Tien-I
• Liu Ru-Gun
• Shue Shau-Lin

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/6902

  composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title