Semiconductor package

Patent metadata

Field	Value
Publication number	US-10756076-B2
Application number	US-201816201361-A
Country	US
Kind code	B2
Filing date	Nov 27, 2018
Priority date	Feb 6, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A semiconductor package includes a package substrate, a logic chip on the package substrate, a memory stack structure on the package substrate and including first and second semiconductor chips stacked along a first direction, and a first bump between the package substrate and the memory stack structure. The logic chip and the memory stack are spaced apart along a second direction, crossing the first direction, on the package substrate. The first semiconductor chip includes a through via electrically connected to the second semiconductor chip, a chip signal pad connected to the through via, and a first redistribution layer electrically connected to the chip signal pad and having an edge signal pad in contact with the first bump. A distance between the logic chip and the edge signal pad along the second direction is less than that between the logic chip and the chip signal pad.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate;
a logic chip on the package substrate;
a memory stack structure on the package substrate, the memory stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip along a first direction, the memory stack structure being spaced apart from the logic chip along a second direction, crossing the first direction; and
a first bump between the package substrate and the memory stack structure,
wherein the first semiconductor chip includes:
a first area adjacent to the logic chip and a second area on a center of the first semiconductor chip;
a through via electrically connected to the second semiconductor chip;
a chip signal pad connected to the through via; and
a first redistribution layer electrically connected to the chip signal pad and having an edge signal pad in contact with the first bump, wherein
along the second direction, a distance between the logic chip and the edge signal pad is less than a distance between the logic chip and the chip signal pad,
the edge signal pad is on the first area, and
the chip signal pad is on the second area.

2. The semiconductor package as claimed in claim 1 , wherein:
the chip signal pad includes a plurality of chip signal pads,
a first signal pad of the plurality of chip signal pads is on the first area, and
a second signal pad of the plurality of chip signal pads is on the second area.

3. The semiconductor package as claimed in claim 1 , wherein:
the first semiconductor chip further has a third area,
the second area is in between the first area and the second area along the second direction,
the first redistribution layer further includes an edge power pad that is connected to the package substrate and is supplied with a power voltage or a ground voltage,
the edge power pad being on the third area.

4. The semiconductor package as claimed in claim 1 , wherein the first redistribution layer is spaced apart from the memory stack structure along the first direction.

5. The semiconductor package as claimed in claim 1 , wherein the first redistribution layer further includes a conductive line that extends from the chip signal pad toward the edge signal pad along the second direction, and electrically connects the chip signal pad and the edge signal pad to each other.

6. The semiconductor package as claimed in claim 1 , wherein the package substrate includes a routing line through which an input/output signal is transmitted between the logic chip and the edge signal pad.

7. The semiconductor package as claimed in claim 1 , wherein:
the second semiconductor chip includes a second redistribution layer whose structure is substantially the same as that of the first redistribution layer, and
an edge signal pad of the second redistribution layer is a dummy pad.

8. The semiconductor package as claimed in claim 7 , wherein:
the first bump is between the package substrate and the edge signal pad;
the memory stack structure further includes a second bump between the first semiconductor chip and the second semiconductor chip, and
a chip signal pad on a center of the second semiconductor chip, spaced apart from the edge signal pad of the second redistribution layer along the second direction, is in contact with the second bump.

9. The semiconductor package as claimed in claim 1 , further comprising a second bump between the package substrate and the logic chip, wherein
the logic chip has a first sidewall facing the memory stack structure,
the logic chip includes a logic signal pad adjacent to the first sidewall and in contact with the second bump is attached, and
the logic signal pad and the edge signal pad are electrically connected to each other through the package substrate.

10. A semiconductor package, comprising:
a package substrate including a routing line;
a logic chip on the package substrate;
a memory stack structure on the package substrate, the memory stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip along a first direction, the memory stack structure being spaced apart from the logic chip along a second direction, crossing the first direction, wherein:
a first sidewall of the logic chip faces a second sidewall of the first semiconductor chip along the second direction,
the logic chip includes a logic signal pad adjacent to the first sidewall,
the first semiconductor chip includes:
a through via electrically connected to the second semiconductor chip;
a chip signal pad connected to the through via; and
a first redistribution layer electrically connected to the chip signal pad and having an edge signal pad adjacent to the second sidewall, and

the logic signal pad and the edge signal pad are electrically connected to each other through the routing line; and
a first bump between the package substrate and the edge signal pad, wherein:
the first semiconductor chip has a first area adjacent to the second sidewall and a second area at a center of the first semiconductor chip,
the edge signal pad is on the first area, and
the first bump is spaced apart from the second area along the second direction.

11. The semiconductor package as claimed in claim 10 , further comprising an insulating material between the package substrate and the second area of the first semiconductor chip.

12. The semiconductor package as claimed in claim 10 , wherein the first redistribution layer further includes a conductive line that extends from the chip signal pad toward the edge signal pad along the second direction that electrically connects the chip signal pad and the edge signal pad to each other.

13. The semiconductor package as claimed in claim 10 , wherein:
the second semiconductor chip includes a second redistribution layer whose structure is substantially the same as that of the first redistribution layer, and
an edge signal pad of the second redistribution layer is a dummy pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yonghoon

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title