Input circuit of three-dimensional semiconductor apparatus capable of enabling testing and direct access

Patent metadata

Field	Value
Publication number	US-9589670-B2
Application number	US-201514634167-A
Country	US
Kind code	B2
Filing date	Feb 27, 2015
Priority date	Dec 5, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

An input circuit of a semiconductor apparatus may include a first input buffer configured to receive a signal through a test input terminal and to output a first input signal, a second input buffer configured to receive a signal through a normal input terminal and to output a second input signal. The input circuit of the semiconductor apparatus may include a switching unit configured to transfer the signal inputted through the test input terminal to the second input buffer according to a test mode signal. The input circuit of the semiconductor apparatus may include a comparison unit configured to compare the first input signal with the second input signal and to generate a comparison signal, and a storage unit configured to store the comparison signal.

First claim

What is claimed is:

1. A semiconductor system comprising:
a package substrate configured with a plurality of test input terminals positioned below the package substrate;
an interposer coupled to an upper portion of the package substrate;
a memory module coupled to an upper portion of the interposer and including a plurality of normal input terminals, a normal mode circuit coupled to the plurality of normal input terminals, and a direct access mode circuit coupled to the plurality of test input terminals; and
a memory controller located on the interposer and coupled to the memory module,
wherein the memory module is configured to test an input circuit coupled between the plurality of normal input terminals and the normal mode circuit by supplying a test signal inputted from the test input terminals to the input circuit.

2. The semiconductor system according to claim 1 , wherein the test input terminal includes a direct access ball.

3. The semiconductor system according to claim 1 ,
wherein the memory module includes a plurality of stacked dies, and
wherein the plurality of dies are electrically coupled to one another through a plurality of through electrodes.

4. The semiconductor system according to claim 1 ,
wherein the memory module includes a plurality of stacked dies, and
wherein the plurality of dies are configured to transmit data, a command, and an address through a plurality of through electrodes.

5. The semiconductor system according to claim 1 ,
wherein the memory module includes a plurality of stacked dies, and
wherein one of the plurality of dies is configured to test whether the input circuit is normally operating.

6. The semiconductor system according to claim 1 ,
wherein the memory module includes a plurality of stacked dies,
wherein the plurality of dies comprise:
a base die coupled to the upper portion of the interposer; and
a plurality of core dies stacked on the base die, and
wherein the base die is configured to test whether the input circuit is normally operating.

7. The semiconductor system according to claim 1 ,
wherein the memory module includes a plurality of stacked dies,
wherein the plurality of dies include a base die coupled to the upper portion of the interposer,
wherein the base die includes a physical area, and
wherein the memory controller includes
a second physical area coupled to the physical area of the base die through the interposer.

8. The semiconductor system according to claim 1 ,
wherein the memory module comprises:
a first input buffer configured to receive the test signal through the test input terminal and to output a first input signal;
a second input buffer configured to receive a normal signal through the normal input terminal and to output a second input signal;
a switching unit configured to transfer the test signal inputted through the test input terminal to the second input buffer according to a test mode signal;
a comparison unit configured to compare the first input signal with the second input signal and to generate a comparison signal; and
a storage unit configured to store the comparison signal.

9. The semiconductor system according to claim 8 , wherein the normal input terminal includes a micro bump located within the memory module.

10. The semiconductor system according to claim 8 ,
wherein the direct access mode circuit is configured to perform an operation related to a direct access mode according to the first input signal; and
wherein the normal mode circuit is configured to perform data write or read related to a normal mode according to the second input signal.

11. The semiconductor system according to claim 8 , wherein the comparison unit is configured to perform a XNOR logic.

12. The semiconductor system according to claim 8 , wherein the storage unit includes a register accessible from an exterior of the semiconductor system.

Assignees

• Sk Hynix Inc

Inventors

• Kim Dae Suk

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title

• H03K5/22

  Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral (indicating phase difference of two cyclic pulse trains G01R25/00) · CPC title