Semiconductor packages including interconnectors and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9941253-B1
Application number	US-201715597484-A
Country	US
Kind code	B1
Filing date	May 17, 2017
Priority date	Nov 17, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A semiconductor package and or method of fabricating a semiconductor package may be provided. The semiconductor package may include a package substrate. The semiconductor package may include a first semiconductor die coupled to the package substrate by first interconnectors. The semiconductor package may include a second semiconductor die coupled to the first semiconductor die by second interconnectors. The second semiconductor die may be coupled to the substrate.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate;
a first semiconductor die coupled to the package substrate by first interconnectors;
a second semiconductor die configured to have an edge region overlapping with an edge region of the first semiconductor die, the second semiconductor die coupled to the edge region of the first semiconductor by second interconnectors, and the second semiconductor die coupled to the package substrate by third interconnectors; and
a third semiconductor die stacked on the second semiconductor die,
wherein a length of the first interconnectors is different from a length of the second interconnectors, and
wherein the second semiconductor die has a width which is greater than a width of the third semiconductor die.

2. The semiconductor package of claim 1 , wherein the second interconnectors are bumps having a length which is less than a length of the first interconnectors.

3. The semiconductor package of claim 1 , wherein the second interconnectors are disposed to vertically couple the edge region of the first semiconductor die to the edge region of the second semiconductor die.

4. The semiconductor package of claim 1 ,
wherein the edge region of the second semiconductor die is disposed between the edge region of the first semiconductor die and the package substrate; and
wherein the first interconnectors are disposed to pass by a sidewall of the edge region of the second semiconductor die and are spaced apart from the sidewall of the edge region of the second semiconductor die.

5. A semiconductor package comprising:
a package substrate;
a first semiconductor die coupled to the package substrate by first interconnectors;
a second semiconductor die configured to have an edge region overlapping with an edge region of the first semiconductor die, the second semiconductor die coupled to the edge region of the first semiconductor by second interconnectors, and the second semiconductor die coupled to the package substrate by third interconnectors; and
a third semiconductor die stacked on the second semiconductor die,
wherein a length of the first interconnectors is different from a length of the second interconnectors,
wherein the second semiconductor die includes:
first through vias disposed in the edge region of the second semiconductor die and connected to the second interconnectors; and
second through vias disposed in the second semiconductor die spaced apart from the first through vias and connected to the third semiconductor die, and
wherein the second semiconductor die further includes a first redistributed line connecting at least one of the first through vias to at least one of the second through vias.

6. The semiconductor package of claim 5 , wherein the second semiconductor die further includes a second redistributed line connecting at least one of the second through vias to at least one of the third interconnectors that do not overlap with the second through vias.

7. The semiconductor package of claim 5 , wherein the second semiconductor die further includes a first interface region having a physical layer that is disposed to overlap with the first through vias and to exchange data with the first semiconductor die.

8. The semiconductor package of claim 7 , wherein the first semiconductor die includes a second interface region having a physical layer that is disposed in the edge region of the first semiconductor die to overlap with the first interface region and to exchange data with the second semiconductor die.

9. The semiconductor package of claim 5 , further comprising fourth interconnectors that respectively overlap with the second through vias to electrically connect the second through vias to the third semiconductor die.

10. The semiconductor package of claim 9 , wherein the third semiconductor die includes third through vias that are disposed to overlap with the second through vias and are electrically connected to the fourth interconnectors.

11. The semiconductor package of claim 1 , wherein the third semiconductor die is disposed on the second semiconductor die so that the edge region of the second semiconductor die laterally protrudes further than a sidewall of the third semiconductor die.

12. The semiconductor package of claim 1 , wherein the third interconnectors are arrayed to have a pitch which is greater than a pitch of the second interconnectors.

13. The semiconductor package of claim 1 , wherein the third interconnectors are substantially uniformly distributed on an entire portion of a surface of the second semiconductor die.

14. A semiconductor package comprising:
a package substrate;
a first semiconductor die coupled to the package substrate by first interconnectors;
a second semiconductor die configured to have an edge region overlapping with an edge region of the first semiconductor die, the second semiconductor die coupled to the edge region of the first semiconductor by second interconnectors, and the second semiconductor die coupled to the package substrate by third interconnectors; and
a third semiconductor die stacked on the second semiconductor die,
wherein a length of the first interconnectors is different from a length of the second interconnectors, and
wherein the third semiconductor die is a memory die including a memory cell region that stores data which are transmitted to the first semiconductor die.

15. The semiconductor package of claim 14 , wherein the second semiconductor die includes a memory cell region that stores data which are transmitted to the first semiconductor die.

16. A semiconductor package comprising:
a package substrate;
a first semiconductor die coupled to the package substrate by first interconnectors;
a second semiconductor die configured to have an edge region overlapping with an edge region of the first semiconductor die, the second semiconductor die coupled to the edge region of the first semiconductor by second interconnectors, and the second semiconductor die coupled to the package substrate by third interconnectors;
a third semiconductor die stacked on the second semiconductor die; and an encapsulant layer that substantially covers sidewalls of the second and third semiconductor dies and substantially exposes an upper surface of the first semiconductor die.

17. A semiconductor package comprising:
a package substrate;
a first semiconductor die coupled to the package substrate by first interconnectors;
a second semiconductor die configured to have an edge region overlapping with a first edge region of the first semiconductor die, the second semiconductor die coupled to the first edge region of the first semiconductor by second interconnectors, and the second semiconductor die coupled to the package substrate by third interconnectors; and
a third semiconductor die configured to have an edge region overlapping with a second edge region of the first semiconductor die, the third semiconductor die coupled to the second edge region of the first semiconductor by third interconnectors, and the third semiconductor die coupled to the package substrate by fourth interconnectors,
wherein the first semiconductor die is coupled to the package substrate by the first interconnectors disposed on a central region of the first semiconductor die between the first and second edge regions of the first semiconductor die and passing through an empty space between the second and third semiconductor dies.

Assignees

• Sk Hynix Inc

Inventors

• Jung Yeon Seung
• Park Jin Woo
• Hong Joo Wan

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title