Semiconductor package device

Patent metadata

Field	Value
Publication number	US-9685422-B2
Application number	US-201514956695-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Sep 18, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A semiconductor package may include a first chip located over a substrate. The semiconductor package may include a second chip located over the substrate and adjacent to the first chip. The semiconductor package may include a test micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to an external connection member through a first path. The semiconductor package may include a normal micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to the second chip through a second path.

First claim

What is claimed is:

1. A semiconductor package device comprising:
a first chip located over a substrate;
a second chip located over the substrate and adjacent to the first chip on the same layer as in the first chip;
a test micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to an external connection member through a first path;
a normal micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to the second chip through a second path;
a molding member molded into a predetermined region of an outer wall of the first chip, and formed over the test micro-bump and the normal micro-bump;
a plurality of micro-bumps located between a lower region of the second chip and the substrate;
a first re-distribution layer (RDL) configured to couple the test micro-bump to the first chip through the molding member; and
a second re-distribution layer (RDL) configured to couple the normal micro-bump to the plurality of micro-bumps,
wherein the first re-distribution layer (RDL) is directly connected to a lower region of the molding member and the first chip.

2. The semiconductor package device according to claim 1 , wherein the second chip is a System On Chip (SOC).

3. The semiconductor package device according to claim 1 , wherein the first chip includes a Dynamic Random Access Memory (DRAM).

4. The semiconductor package device according to claim 1 , further comprising:
a first re-distribution layer (RDL) configured to couple the normal micro-bump to the first chip through the molding member.

5. The semiconductor package device according to claim 1 , wherein the test micro-bump is configured for usage in a Direct Access (DA) test mode in which the first chip is directly tested through the first path.

6. The semiconductor package device according to claim 1 , further comprising:
a wafer test pad arranged in a lower contour region of the first chip.

7. The semiconductor package device according to claim 6 , wherein the wafer test pad is coupled to the test micro-bump through a re-distribution layer (RDL).

8. The semiconductor package device according to claim 6 , wherein the wafer test pad is configured to be used to perform probing during wafer-level testing.

9. The semiconductor package device according to claim 1 , wherein the external connection member comprises a direct access ball.

10. The semiconductor package device according to claim 1 , wherein the substrate comprises a printed circuit board.

11. A semiconductor package device comprising:
a substrate;
a first chip;
a second chip located under the first chip and located over the substrate;
a first wafer test pad located in an upper edge region of the first chip; and
a connection member formed below the substrate, and electrically coupled to the first wafer test pad,
wherein the first wafer test pad is formed in an upper edge region adjacent an outer wall of the chip,
wherein the first wafer test pad is directly connected to the substrate through wire bonding.

12. The semiconductor package device according to claim 11 , wherein the second chip is a System On Chip (SOC).

13. The semiconductor package device according to claim 11 , wherein the first chip includes a Dynamic Random Access Memory (DRAM).

14. The semiconductor package device according to claim 11 , wherein the first chip is electrically coupled to the second chip through a micro-bump.

15. The semiconductor package device according to claim 11 , further comprising:
a plurality of micro-bumps coupled between the second chip and the substrate.

16. The semiconductor package device according to claim 11 , further comprising:
a third chip located over the second chip, and arranged adjacent to the first chip.

17. The semiconductor package device according to claim 16 , wherein the third chip includes a Dynamic Random Access Memory (DRAM).

18. The semiconductor package device according to claim 16 , further comprising:
a second wafer test pad formed in an upper edge region of the third chip, and coupled to the substrate through wire bonding.

19. The semiconductor package device according to claim 18 , wherein:
the first wafer test pad is formed in an upper left edge region of the first chip; and
the second wafer test pad is formed in an upper right edge region of the third chip,
whereby the first wafer test pad is arranged adjacent to the second wafer test pad.

20. The semiconductor package device according to claim 18 , wherein:
the first wafer test pad is formed in an upper edge region of the first chip adjacent an outer wall of the first chip; and
the second wafer test pad is formed in an upper edge region of the third chip adjacent an outer wall of the third chip,
whereby the first wafer test pad is arranged adjacent to an outer wall of the second chip and the second wafer test pad is arranged adjacent to another outer wall of the second chip opposite the outer wall of the second chip.

21. The semiconductor package device according to claim 18 , further comprising:
a first re-distribution layer (RDL) coupled to wire bonding and configured to interconnect the first wafer test pad and the substrate; and
a second re-distribution layer (RDL) coupled to wire bonding and configured to interconnect the second wafer test pad and the substrate.

Assignees

• Sk Hynix Inc

Inventors

• Lee Tae Yong

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title