Three-dimensional memory device containing bit line switches

Patent metadata

Field	Value
Publication number	US-10734080-B2
Application number	US-201816213382-A
Country	US
Kind code	B2
Filing date	Dec 7, 2018
Priority date	Dec 7, 2018
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

First claim

What is claimed is:

1. A circuit, comprising:
a first memory block region and a second memory block region located in a first semiconductor chip;
a first switch located in a second semiconductor chip configured to bond to the first semiconductor chip;
a second switch located in the second semiconductor chip;
a first portion of a first bit line traversing the first memory block region and electrically connected to the first switch;
a second portion of the first bit line traversing the second memory block region and electrically connected to the second switch; and
a sense amplifier electrically connected to the first portion of the first bit line through the first switch, wherein the sense amplifier is electrically connected to the second portion of the first bit line through the second switch.

2. The circuit of claim 1 , wherein the sense amplifier is located in the second semiconductor chip, and the first semiconductor chip comprises a first semiconductor substrate that is vertically spaced from the second semiconductor chip by the first memory block region, the second memory block region, the first portion of the first bit line, and the second portion of the first bit line.

3. The circuit of claim 2 , further comprising:
a first electrically conductive path electrically connecting the first switch and the first portion of the first bit line through the first semiconductor chip and the second semiconductor chip; and
a second electrically conductive path electrically connecting the second switch and the second portion of the first bit line through the first semiconductor chip and the second semiconductor chip.

4. The circuit of claim 3 , wherein:
the first electrically conductive path comprises a first bonding structure located at an interface between the first semiconductor chip and the second semiconductor chip; and
the second electrically conductive path comprises a second bonding structure located at the interface between the first semiconductor chip and the second semiconductor chip.

5. The circuit of claim 4 , wherein:
the sense amplifier is electrically connected to the first portion of the first bit line through both the first electrically conductive path and the first switch; and
the sense amplifier is electrically connected to the second portion of the first bit line through both the second electrically conductive path and the second switch.

6. The circuit of claim 4 , wherein:
the first switch comprises a first transistor having a first channel in a semiconductor substrate of the second semiconductor chip and a first gate electrode located between the first channel and the first bonding structure; and
the second switch comprises a second transistor having a second channel in the semiconductor substrate of the second semiconductor chip and a second gate electrode located between the second channel and the second bonding structure.

7. A method of operating the circuit of claim 1 , comprising:
turning on the first switch while the second switch is turned off; and
providing a first current from the sense amplifier to the first portion of the first bit line without providing the first current from the sense amplifier to the second portion of the first bit line to perform a read operation, a write operation, or an erase operation on at least one memory cell located in the first memory block.

8. The method of claim 7 , further comprising:
turning off the first switch;

turning on second switch; and
providing a second current from the sense amplifier to the second portion of the first bit line without providing the second current from the sense amplifier to the first portion of the first bit line to perform the read operation, the write operation, or the erase operation on at least one memory cell located in the second memory block.

9. The circuit of claim 1 , wherein:
the first memory block region comprises a first alternating stack of first insulating layers and first electrically conductive layers;
the second memory block region comprise a second alternating stack of second insulating layers and second electrically conductive layers;
the first portion of the first bit line laterally traverses the first memory block region within the first semiconductor chip between the first alternating stack and the second semiconductor chip; and
the second portion of the first bit line laterally traverses the second memory block region within the first semiconductor chip between the second alternating stack and the second semiconductor chip.

10. The circuit of claim 1 , wherein:
the first semiconductor chip comprises a first semiconductor substrate on which the first memory block region and the second memory block region are located;
the second semiconductor chip comprises a second semiconductor substrate on which the first switch and the second switch are located; and
the first semiconductor substrate is vertically spaced from the second semiconductor substrate by the first memory block region and the second memory block region.

11. A circuit, comprising:
a first memory block region and a second memory block region located in a first semiconductor chip;
a first switch located in a second semiconductor chip configured to bond to the first semiconductor chip;
a second switch located in the second semiconductor chip;
a first portion of a first bit line traversing the first memory block region and electrically connected to the first switch;
a second portion of the first bit line traversing the second memory block region and electrically connected to the second switch;
a sense amplifier electrically connected to the first portion of the first bit line through the first switch, wherein the sense amplifier is electrically connected to the second portion of the first bit line through the second switch;
a third memory block region;
a third switch;
a fourth switch;
a first portion of a second bit line traversing the first and second memory block regions and electrically connected to the sense amplifier through the third switch; and
a second portion of the second bit line traversing the third memory block region and electrically connected to the sense amplifier through the fourth switch.

12. The circuit of claim 11 , wherein:
the second portion of the first bit line also traverses the third memory block region; and
an additional switch electrically connected to the second portion of the first bit line between the second and the third memory block regions.

13. A device, comprising:
first memory stack structures extending through a first alternating stack of first insulating layers and first electrically conductive layers in a first memory block region of a first semiconductor chip;
second memory stack structures extending through a second alternating stack of second insulating layers and second electrically conductive layers in a second memory block region of the first semiconductor chip, wherein each of the first and second memory stack structures comprises a respective vertical semiconductor channel and a respective memory film;
a first switch located in a second semiconductor chip that is bonded to the first semiconductor chip and electrically connected to the first memory stack structures via a first portion of a first bit line in the first semiconductor chip;
a second switch located in the second semiconductor chip and electrically connected to the second memory stack structures via a second portion of the first bit line in the first semiconductor chip; and
a sense amplifier located in the second semiconductor chip and electrically connected to the first switch and to the second switch.

Assignees

• Sandisk Technologies Llc

Inventors

• Chibvongodze Hardwell
• Nishikawa Masatoshi
• Ookuma Naoki
• Ariki Takuya
• Miwa Toru

Classifications

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title