Memory system for adjusting clock frequency

Patent metadata

Field	Value
Publication number	US-10734043-B2
Application number	US-201816054633-A
Country	US
Kind code	B2
Filing date	Aug 3, 2018
Priority date	Dec 11, 2017
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.

First claim

What is claimed is:

1. A memory system comprising:
a logic circuit configured to determine a first frequency of a first clock using a first signal and to generate a second signal for adjusting the first frequency of the first clock;
a phase locked loop (PLL) circuit configured to receive a second clock, and to generate the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal; and
a signal generator configured to receive the second clock, and generate a third signal for adjusting the second frequency of the second clock using the second clock,
wherein, when a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.

2. The memory system of claim 1 , wherein the signal generator is configured to determine the second frequency of the second clock, based on a noise included in the second clock.

3. The memory system of claim 1 , further comprising:
a memory cell array configured to output a data signal according to control by the logic circuit.

4. The memory system of claim 3 , wherein the memory cell array is configured to store an identifier indicating information associated with a ratio between the second frequency of the second clock and a frequency of the data signal.

5. The memory system of claim 4 ,
wherein the signal generator is further configured to determine the frequency of the data signal,
wherein the first signal indicates information associated with the frequency of the data signal, and
wherein the logic circuit is configured to determine the first frequency of the first clock based on the frequency of the data signal.

6. The memory system of claim 5 , wherein the signal generator is configured to determine the frequency of the data signal as one of frequencies determined based on the identifier.

7. The memory system of claim 5 , wherein the frequency of the data signal is determined according to a request of a host, and
wherein the logic circuit is configured to determine the first frequency of the first clock to be identical to the frequency of the data signal determined by the signal generator.

8. The memory system of claim 4 , wherein the logic circuit generates a fourth signal for controlling the memory cell array,
wherein the fourth signal indicates an address of a memory cell of the memory cell array where the identifier is stored, and
wherein the memory cell array is configured to output the data signal indicating the identifier in response to the fourth signal.

9. The memory system of claim 1 , wherein the PLL circuit includes:
a divider configured to adjust the first frequency of the first clock according to a division ratio.

10. The memory system of claim 9 , wherein the division ratio is adjusted using the second signal, and
wherein the divider is configured to output the first clock having the first frequency determined by the logic circuit, using the second signal.

11. The memory system of claim 10 , further comprising:
a memory cell array configured to output a data signal under control of the logic circuit and to store an identifier indicating information about a ratio between the second frequency of the second clock and a frequency of the data signal,
wherein the division ratio corresponds to the ratio between the second frequency of the second clock and the frequency of the data signal.

12. A memory system comprising:
a logic circuit configured to determine a first frequency of a first clock using a first signal, and to generate a second signal for adjusting the first frequency of the first clock and a third signal associated with a data signal;
a phase locked loop (PLL) circuit configured to receive the second signal from the logic circuit and to generate the first clock using a second clock and the second signal; and
a memory cell array configured to store an identifier, to receive the third signal from the logic circuit, to output the data signal indicating the identifier using the third signal,
wherein, when a frequency of the data signal varies, the logic circuit determines the first frequency of the first clock such that a ratio between the first frequency of the first clock and the frequency of the data signal is uniform, and
wherein the first frequency of the first clock determined by the logic circuit is one of frequencies determined based on the identifier, and
wherein the third signal indicates an address of the identifier stored in the memory cell array.

13. The memory system of claim 12 , further comprising:
a signal generator configured to:
determine the first frequency of the first clock as one of the frequencies determined by the identifier using the second clock, and
generate a fourth signal for adjusting a second frequency of the second clock.

14. The memory system of claim 13 , wherein, when a magnitude of noise included in the second clock is not smaller than a reference value, the signal generator is configured to adjust the second frequency of the second clock to a frequency, which is lower than the second frequency of the second clock, from among the frequencies determined by the identifier.

15. The memory system of claim 14 , wherein the PLL circuit includes:
a divider configured to adjust the first frequency of the first clock according to a division ratio determined using the second signal.

16. The memory system of claim 15 , wherein the divider is configured to output the first clock having the first frequency determined by the logic circuit according to the division ratio adjusted by the second signal.

17. The memory system of claim 16 , wherein a number of division ratios provided by the divider is identical to a number of the frequencies determined based on the identifier.

18. A memory system comprising:
a logic circuit configured to generate a second signal for adjusting a first frequency of a first clock, using a first signal;
a PLL circuit including a divider having a first division ratio adjusted according to the second signal, wherein the PLL circuit is configured to generate the first clock having the first frequency obtained from a second clock using the first division ratio; and
a memory cell array configured to store a plurality of identifiers including a first identifier, and output a data signal indicating the first identifier,
wherein the first frequency is one of frequencies determined based on the first identifier,
wherein the divider his a plurality of division ratios including the first division ratio, and
wherein the number of the plurality of division ratios is substantially identical to the number of frequencies that may be determined based on the plurality of identifiers.

19. The memory system of claim 18 , wherein the logic circuit is configured to set the first frequency of the first clock to be identical to a frequency of the data signal, using the first signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Young-Ju
• Kang Dong-Seok
• Kwon Hye Jung
• Kim Byungchul
• Bae Seungjun

Classifications

• G06F13/4234

  being a memory bus · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title