Dynamic clock-data phase alignment in a source synchronous interface circuit

Patent metadata

Field	Value
Publication number	US-10218360-B2
Application number	US-201615226037-A
Country	US
Kind code	B2
Filing date	Aug 2, 2016
Priority date	Aug 2, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

First claim

What is claimed is:

1. Clock-data phase alignment circuitry, comprising:
clock phase adjustment circuitry that receives a differential clock with first and second clock signals that are complementary to each other;
a first clock distribution network that receives the first clock signal from the clock phase adjustment circuitry and propagates the first clock signal through a first branch that has a first delay and includes at least one first clock buffer to provide a delayed first clock signal and through a second branch that is parallel to the first branch, has a second delay that is substantially equal to the first delay, and provides a delayed second clock signal;
a first storage circuit that receives the delayed first clock signal and a first data signal and stores the first data signal based on the delayed first clock signal;
a second storage circuit that receives the delayed second clock signal and a second data signal and stores the second data signal based on the delayed second clock signal; and
a second clock distribution network coupled between the first clock distribution network and the clock phase adjustment circuitry, wherein the second clock distribution network receives the delayed first clock signal and propagates the delayed first clock signal through at least one second clock buffer to provide a further delayed first clock signal to the clock phase adjustment circuitry, wherein the first clock distribution network and the second clock distribution network reside externally and separately from the clock phase adjustment circuitry.

2. The clock-data phase alignment circuitry of claim 1 , wherein the second clock distribution network replicates at least a branch of the first clock distribution network.

3. The clock-data phase alignment circuitry of claim 1 , wherein each of the at least first and second clock buffers have a delay of less than half a unit interval (UI).

4. The clock-data phase alignment circuitry of claim 1 , wherein the clock phase adjustment circuitry further comprises:
a first adjustable delay circuit that delays the first clock signal by a first adjusted delay; and
a second adjustable delay circuit that delays the further delayed first clock signal by a second adjusted delay to provide a feedback clock signal.

5. The clock-data phase alignment circuitry of claim 4 , wherein the clock phase adjustment circuitry further comprises:
a phase detector that provides a control signal based on a phase difference between the second clock signal and the feedback clock signal.

6. The clock-data phase alignment circuitry of claim 5 , wherein the clock phase adjustment circuitry further comprises:
a delay control circuit that adjusts the first and second adjusted delays of the first and second adjustable delay circuits respectively based on the control signal.

7. The clock-data phase alignment circuitry of claim 5 , wherein the phase detector further comprises:
a register that provides the control signal by storing the second clock signal based on the feedback signal.

8. The clock-data phase alignment circuitry of claim 7 , wherein the control signal is logic ‘0’ to indicate a desired delay increase and logic ‘1’ to indicate a desired delay decrease.

9. A clock-data phase alignment circuit in an integrated circuit, comprising:
a clock input that receives a differential clock signal having first and second clock signals;
a data input that receives a data signal;
a first clock distribution circuit with a first branch and a second branch that is parallel to the first branch and has substantially the same delay as the first branch, and wherein the first and second branches convey the first clock signal to provide a sampling clock signal;
a second clock distribution circuit with a third branch that is a replica of the first branch, and conveys the sampling clock signal to provide a feedback clock signal;
a clock phase adjustment circuit that controls a predetermined phase shift between the sampling clock signal and the data signal based on the first and second clock signals and the feedback clock signal, wherein the first clock distribution circuit receives a clock signal from the clock phase adjustment circuitry and the second clock distribution circuit provides a delay clock signal to the clock phase adjustment circuit, and wherein the first clock distribution network and the second clock distribution network reside outside of the clock phase adjustment circuitry; and
a storage circuit that receives the data signal from the data input and the sampling clock signal from the first clock distribution circuit and stores the data signal based on the sampling clock signal.

10. The clock-data phase alignment circuit of claim 9 , wherein each of the first and third branches has a respective delay of less than one half of a unit interval (UI).

11. The clock-data phase alignment circuit of claim 9 , further comprising:
at least one clock buffer in the first branch; and
at least one other clock buffer in the third branch.

12. The clock-data phase alignment circuit of claim 9 , wherein the clock phase adjustment circuit further comprises:
a first adjustable delay circuit that delays the first clock signal by a first adjusted delay; and
a second adjustable delay circuit that delays the feedback clock signal by a second adjusted delay.

13. The clock-data phase alignment circuit of claim 12 , wherein the clock phase adjustment circuit further comprises:
a phase detector circuit that generates a phase adjustment signal based on a detected phase difference between the second clock signal and the feedback clock signal delayed by the second adjusted delay; and
a delay control circuit that generates a control signal to adjust the first and second adjusted delays based on the phase adjustment signal.

14. A method for operating clock alignment circuitry, comprising:
receiving, with clock phase adjustment circuitry, a differential clock having first and second clock signals that are complementary to each other;
propagating the first clock signal from the clock phase adjustment circuitry through a first branch that has a first delay and includes at least one first clock buffer in a first clock distribution network to provide a delayed first clock signal;
propagating the first clock signal through a second branch that is parallel to the first branch, includes a same number of clock buffers as the first branch to generate a second delay that is substantially equal to the first delay, and provides a delayed second clock signal;
storing a first data signal based on the delayed first clock signal in a first storage circuit;
storing a second data signal based on the delayed second clock signal in a second storage circuit; and
propagating the delayed first clock signal through at least one second clock buffer in a second clock distribution network that is coupled between the first clock distribution network and the clock phase adjustment circuitry to provide a further delayed first clock signal to the clock phase adjustment circuitry.

15. The method of claim 14 , further comprising:
delaying the delayed first clock signal in the first clock distribution network by less than half a unit interval (UI) relative to the first clock signal; and
delaying the further delayed first clock signal in the second clock distribution network by less than half a unit interval (UI) relative to the delayed first clock signal.

16. The method of claim 14 , further comprising:
using a first adjustable delay circuit in the clock phase adjustment circuitry to delay the first clock signal by a

Assignees

• Altera Corp

Inventors

• Patil Dinesh
• Chan Kok Hong
• Wong Wai Tat
• Khor Chuan Thim

Classifications

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H04L47/56

  implementing delay-aware scheduling · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title