Frequency selection granularity for integrated circuits

Patent metadata

Field	Value
Publication number	US-9343126-B2
Application number	US-201213730607-A
Country	US
Kind code	B2
Filing date	Dec 28, 2012
Priority date	Sep 12, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.

First claim

What is claimed is:

1. An apparatus comprising:
memory device clocking circuitry, comprising:
a frequency multiplier coupled to receive a clock signal and to generate a frequency-multiplied clock signal;
a switching circuit coupled to receive at least two reference clock signals each having a different frequency, the switching circuit to provide a selected one of the at least two reference clock signals in response to a reference select signal;
a phase locked loop (PLL) coupled to receive the frequency-multiplied clock signal and the selected reference clock signal, the PLL to generate an output clock signal based on the frequency-multiplied clock signal and the selected reference clock signal wherein the output clock signal has a frequency specified in a double data rate (DDR) memory standard when a first reference clock signal is selected with the switching circuit and the output clock signal has a frequency greater than specified in the DDR memory standard or a frequency that is in between two frequencies specified in the DDR memory standard, when a second reference clock signal is selected.

2. The apparatus of claim 1 further comprising one or more frequency dividers coupled in series with the frequency multiplier.

3. The apparatus of claim 2 further comprising a plurality of frequency multipliers coupled with the one or more frequency dividers, wherein the frequency multipliers and the frequency dividers are coupled in combination.

4. The apparatus of claim 3 wherein the frequency dividers and the frequency multipliers are selected in response to a value stored in a control register.

5. The apparatus of claim 1 wherein the reference clock signal is selected in response to a value stored in a control register.

6. A system comprising:
a memory device coupled to memory device clocking circuitry, the memory device clocking circuitry, comprising:
a frequency multiplier coupled to receive a clock signal and to generate a frequency-multiplied clock signal;
a switching circuit coupled to receive at least two reference clock signals each having a different frequency, the switching circuit to provide a selection of one of the at least two reference clock signals in response to a reference select signal;
a phase locked loop (PLL) coupled to receive the frequency-multiplied clock signal and the selected reference clock signal, the PLL to generate an output clock signal based on the frequency-multiplied clock signal and the selected reference clock signal wherein the output clock signal has a frequency specified in a double data rate (DDR) memory standard when a first reference clock signal is selected with the switching circuit and the output clock signal has a frequency greater than specified in the DDR memory standard or a frequency that is in between two frequencies specified in the DDR memory standard, when a second reference clock signal is selected.

7. The system of claim 6 further comprising one or more frequency dividers coupled in series with the frequency multiplier.

8. The system of claim 7 further comprising a plurality of frequency multipliers coupled with the one or more frequency dividers, wherein the frequency multipliers and the frequency dividers are coupled in combination.

9. The system of claim 8 wherein the frequency dividers and the frequency multipliers are selected in response to a value stored in a control register.

10. The system of claim 6 wherein the memory device conforms to a double data rate (DDR) standard.

11. The system of claim 6 wherein the reference clock signal is selected in response to a value stored in a control register.

12. A method comprising:
generating a clock signal for a memory device by performing the following:
receiving a clock signal with a frequency multiplier;
generating a frequency-multiplied clock signal with the frequency multiplier;
receiving at least two reference clock signals with a switching circuit each having a different frequency;
providing a selected one of the at least two reference clock signals in response to a reference select signal with the switching circuit;
generating an output clock signal with a phase locked loop (PLL) coupled to receive the frequency-multiplied clock signal and the selected reference clock signal based on the frequency-multiplied clock signal and the selected reference clock signal wherein the output clock signal has a frequency specified in a double data rate (DDR) memory standard when a first reference clock signal is selected with the switching circuit and the output clock signal has a frequency greater than specified in the DDR memory standard or a frequency that is in between two frequencies specified in the DDR memory standard, when a second reference clock signal is selected.

13. The method of claim 12 further comprising providing the output clock signal to at least one memory device.

14. The method of claim 13 wherein the memory device conforms to a double data rate (DDR) standard.

15. The method of claim 13 wherein the reference clock signal is selected in response to a value stored in a control register.

Assignees

• Intel Corp

Inventors

• Baliga Harikrishna B
• Smith Peter J
• Ray Joydeep

Classifications

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• G11C8/18 Primary

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• H03L7/07 Primary

  using several loops, e.g. for redundant clock signal generation · CPC title