Etendue enhancement for light emitting diode subpixels

Patent metadata

Field	Value
Publication number	US-10707374-B2
Application number	US-201816123182-A
Country	US
Kind code	B2
Filing date	Sep 6, 2018
Priority date	Sep 15, 2017
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A method of forming a light emitting device includes forming a growth mask layer including openings on a doped compound semiconductor layer, forming first light emitting diode (LED) subpixels by forming a plurality of active regions and second conductivity type semiconductor material layers employing selective epitaxy processes, and transferring each first LED subpixel to a backplane. An anode contact electrode may be formed on the second conductivity type semiconductor material layers for redundancy. The doped compound semiconductor layer may be patterned with tapered sidewalls to enhance etendue. An optically clear encapsulation matrix may be formed on the doped compound semiconductor material layer to enhance etendue. Lift-off processes may be employed for the active regions. Cracking of the LEDs may be suppressed employing a thick reflector layer.

First claim

The invention claimed is:

1. A semiconductor structure, comprising:
a mesa base semiconductor portion comprising a doped compound semiconductor layer having a top surface on a first side and having a bottom semiconductor surface on a second side that is an opposite side of the first side;
a growth mask layer located on the top surface of the doped compound semiconductor layer and including at least one opening therethrough;
at least one selectively grown epitaxial semiconductor structure extending through the at least one respective opening through the growth mask layer and having a doping of a first conductivity type;
at least one semiconductor layer stack located on a respective selectively grown epitaxial semiconductor structure;
at least one second conductivity type semiconductor material layer having a doping of a second conductivity type located on the at least one semiconductor layer stack;
a dielectric liner layer including a portion that overlies the second conductivity type semiconductor material layer, contacting sidewalls of, and laterally surrounding, the growth mask layer, and contacting sidewalls of, and laterally surrounding, the mesa base semiconductor portion, wherein the dielectric liner extends to a periphery of the bottom semiconductor surface of the mesa base semiconductor portion; and
a reflector layer located over the dielectric liner layer and including sidewall portions that laterally surround the second conductivity type semiconductor material layer, the growth mask layer, and the doped compound semiconductor layer.

2. The semiconductor structure of claim 1 , wherein:
the at least one opening comprises a plurality of openings;
the at least one selectively grown epitaxial semiconductor structure comprises a plurality of selectively grown epitaxial semiconductor structures separated by isolation regions;
each of the selectively grown epitaxial semiconductor structures includes an epitaxial mesa portion and an epitaxial connection portion located in a respective opening in the growth mask layer and connecting a top portion of the doped compound semiconductor layer to a bottom of the epitaxial mesa portion; and
each of the at least one semiconductor layer stack comprises a plurality of semiconductor layer stacks located on a respective epitaxial mesa portion.

3. The semiconductor structure of claim 2 , wherein:
at least one selectively grown epitaxial semiconductor structure comprises a III-nitride compound semiconductor structure;
the growth mask layer comprises aluminum oxide;
a top surface of each epitaxial mesa portion includes a crystallographic c-plane that is parallel to the top surface of the doped compound semiconductor layer; and
a periphery of a bottom surface of each epitaxial mesa portion contacts a top surface of the growth mask layer around the respective opening.

4. The semiconductor structure of claim 2 , wherein:
each epitaxial mesa portion has tapered sidewalls;
bottom edges of the tapered sidewalls are laterally offset outward from a periphery of a respective opening through the growth mask layer by an average lateral offset distance;
a ratio of a maximum lateral dimension of the respective opening through the growth mask layer to the average lateral offset distance is greater than 2; and
each epitaxial mesa portion has a width ranging from 1 to 100 microns and a length ranging from 1 to 100 microns.

5. The semiconductor structure of claim 2 , wherein:
the semiconductor structure includes at least one light emitting diode (LED);
each of the at least one semiconductor layer stack comprises an active region that includes an optically active compound semiconductor layer stack configured to emit light.

6. A light emitting device comprising the semiconductor structure of claim 5 , wherein:
sidewalls of the doped compound semiconductor layer are vertical or tapered, and contacts the dielectric liner layer; and
the light emitting device further comprises at least one top contact electrode that overlies, and is electrically shorted to, each of the at least one second conductivity type semiconductor material layer.

7. The light emitting device of claim 6 , wherein:
the dielectric liner layer laterally surrounds the top contact electrode and overlies a peripheral portion of the top contact electrode; and
the reflector layer laterally surrounds the top contact electrode and the dielectric liner layer and overlies the peripheral portion of the top contact electrode.

8. The light emitting device of claim 7 , wherein:
the dielectric liner layer includes an opening over the top contact electrode;
the reflector layer includes an opening over the top contact electrode; and
the opening through the dielectric liner layer and the opening through the reflector layer are vertically coincident.

9. The light emitting device of claim 6 , further comprising a conductive bonding structure located within an opening through the reflector layer and bonded to the top contact electrode.

10. A direct view display device, comprising:
a plurality LEDs of claim 6 arranged as a two-dimensional array; and
a backplane comprising metal interconnect structures therein or thereupon;
wherein each of the plurality of LEDs is electrically connected to a respective one of the metal interconnect structures and constitutes a first subpixel which emits light at a first peak wavelength of a respective pixel of the direct view display device.

11. The direct view display device of claim 10 , wherein:
the respective pixel further comprises a second subpixel comprising a second LED which emits light at a second peak wavelength different from the first peak wavelength, and a third subpixel comprising a third LED which emits light at a third peak wavelength different from the first and the second peak wavelengths; and
the direct view display is used in a smart phone, television, augmented reality display, virtual reality display, computer screen, large area display or a watch.

12. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises power semiconductor devices selected from diodes, thyristors, triacs, bipolar junction transistors, power metal oxide semiconductor field effect transistors (MOSFETs), and insulated-gate bipolar transistors.

13. The semiconductor structure of claim 1 , wherein the sidewalls of the mesa base semiconductor portion have a respective taper angle such that a horizontal cross-sectional area along a horizontal plane that is parallel to an interface between the mesa base semiconductor portion and the growth mask layer increases with a vertical distance from the interface between the mesa base semiconductor portion and the growth mask layer.

14. A method of forming a semiconductor structure, comprising:
forming a growth mask layer including openings therethrough on a top surface of a doped compound semiconductor layer located over a substrate;
forming a plurality of selectively grown epitaxial semiconductor structures extending through a respective opening through the growth mask layer and having a doping of a first conductivity type;
forming a plurality of semiconductor layer stacks on a respective selectively grown epitaxial semiconductor structure;
forming at least one second conductivity type semiconductor material layer having a doping of a second conductivity type and on the plurality of semiconductor layer stacks;
patterning the growth mask layer and the doped compound semiconductor layer, wherein discrete mesa base semiconductor portions including a respective patterned portion of the doped compound semiconductor are formed;
forming

Assignees

• Glo Ab

Inventors

• Danesh Fariba
• Leung Benjamin
• Lau Tsun
• Tezcan Zulal
• Tsai Miao-Chan
• Batres Max
• Cich Michael Joseph

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/0363

  of optical field-shaping means · CPC title

• H10H20/034

  of coatings · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title