Semiconductor device including gate channel having adjusted threshold voltage

Patent metadata

Field	Value
Publication number	US-9530699-B2
Application number	US-201514984231-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Apr 30, 2014
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.

First claim

What is claimed is:

1. A method of controlling a voltage threshold of a semiconductor device, the method comprising:
forming an nFET region on a semiconductor substrate, and at least one first semiconductor fin having a fin thickness on the nFET region, the at least one first semiconductor fin having an nFET channel region interposed between a pair of nFET source/drain regions;
forming a plurality of pFET regions on the semiconductor substrate, and forming a second semiconductor fin on each pFET region, the second semiconductor fin having a pFET channel region interposed between a pair of pFET source/drain regions; and
forming a plurality of epitaxial liners having different doping concentrations with respect to one another, each epitaxial liner formed in a respective pFET region such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel region of a respective second semiconductor fin, the epitaxial liners including an etched pFET channel portion,
wherein a combination of the etched pFET channel portion and the epitaxial liners defines a combined thickness that is equal to the fin thickness of the at least one first semiconductor fin.

2. The method of claim 1 , wherein the epitaxial liners have different concentrations of SiGe to define the different first and second threshold voltages.

3. The method of claim 2 , further comprising forming a first pFET including a first epitaxial liner having a first concentration of SiGe, and forming a second pFET including a second epitaxial liner having a second concentration of SiGe that is less than the first concentration.

4. The method of claim 3 , wherein the first epitaxial liner has a 75% concentration of SiGe, and the second epitaxial liner has a 50% concentration of SiGe.

5. The method of claim 4 , further comprising forming a third pFET region including a third epitaxial liner having a 25% concentration of SiGe, and a fourth pFET region that excludes a SiGe liner.

6. The method of claim 5 , wherein each of the first pFET region, the second pFET region, the third pFET region, and the fourth pFET region have a different voltage threshold with respect to one another.

Assignees

• IBM

Inventors

• Kerber Pranita
• Ouyang Qiqing C
• Reznicek Alexander

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D86/215

  comprising FinFETs · CPC title