Semiconductor device and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-9087844-B2
Application number	US-201313930187-A
Country	US
Kind code	B2
Filing date	Jun 28, 2013
Priority date	Aug 28, 2012
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

A semiconductor device includes a lower conductor having a lower conductor sidewall, a barrier film having a barrier film sidewall formed directly on the lower conductor sidewall, and a via formed on a top surface of the lower conductor. A top portion of the barrier film sidewall is recessed, such that a top surface of the barrier film sidewall is at a level lower than the top surface of the lower conductor.

First claim

What is claimed is:

1. A semiconductor device comprising:
a lower conductor having a lower conductor sidewall surface, and a top surface contiguous with the lower conductor sidewall surface, the top surface including an edge portion and a central portion;
a barrier film having a barrier film sidewall disposed directly on the lower conductor sidewall surface; and
a via disposed on the top surface of the lower conductor,
wherein the lower conductor sidewall surface and the edge portion of the top surface of the lower conductor meet at a point, a top surface of the barrier film sidewall intersects the lower conductor at the point at which the lower conductor sidewall surface and the edge portion of the top surface of the lower conductor meet, the edge portion of the top surface of the lower conductor extends in an upward direction directly from the point at which the lower conductor sidewall surface and the edge portion of the top surface of the lower conductor meet, and the top surface of the barrier film sidewall is disposed at a level lower than that of the central portion of the top surface of the lower conductor.

2. The semiconductor device of claim 1 , further comprising:
a first insulation film surrounding a combination of the lower conductor and the barrier film, wherein a recessed region exists above the top surface of the barrier film sidewall and in a portion of the first insulation film proximate the top surface of the barrier film sidewall.

3. The semiconductor device of claim 2 , wherein the recessed region has a width that is upwardly increasing from the top surface of the barrier film.

4. The semiconductor device of claim 3 , wherein the via extends to completely fill the recessed region.

5. The semiconductor device of claim 1 , wherein the width of the lower conductor, in a first direction at the point at which the lower conductor sidewall surface and the edge portion of the top surface of the lower conductor meet, is less than or equal to the width of the via in the first direction between opposite side surfaces at a bottom portion of the via.

6. The semiconductor device of claim 1 , further comprising:
a first upper conductor disposed directly on the via and having opposing sidewall surfaces that vertically align with respective opposing sidewall surfaces of the via.

7. The semiconductor device of claim 6 , further comprising:
a second upper conductor arranged in parallel with the first upper conductor and separated from the first upper conductor by a pitch that ranges from between about 10 nm to about 100 nm.

8. The semiconductor device of claim 6 , wherein the via is a dual damascene via.

9. The semiconductor device of claim 1 , wherein the barrier film comprises at least one of Ti and TiN.

10. The semiconductor device of claim 1 , wherein the edge portion of the top surface of the lower conductor is convex.

11. A semiconductor device comprising:
a metal layer including a first lower conductor and a second lower conductor spaced laterally from each other,
the first lower conductor having first opposite lower conductor sidewall surfaces and a top surface,
the top surface of the first lower conductor having an edge portion and a central portion, and
the second lower conductor having second opposite lower conductor sidewall surfaces and a top surface;
a first barrier film having first barrier film sidewalls directly on the first opposite lower conductor sidewall surfaces, respectively;
a second barrier film having second barrier film sidewalls directly on the second opposite lower conductor sidewall surfaces, respectively; and
a via disposed on the top surface of the first lower conductor, and
wherein a top surface of at least one of the first barrier film sidewalls is disposed at a level lower than that of the central portion of the top surface of the first lower conductor, and
top surfaces of the second barrier film sidewalls are disposed at the same level, and
the top surface of said at least one of the first barrier film sidewalls is disposed at a level lower than that of each of the top surfaces of the second barrier film sidewalls.

12. The semiconductor device of claim 11 , wherein the top surfaces of the second barrier film sidewalls are at a same level as the central portion of the top surface of the first lower conductor.

13. The semiconductor device of claim 11 , further comprising:
a first insulation film surrounding a first combination of the first lower conductor and the first barrier film, and surrounding a second combination of the second lower conductor and the second barrier film,
wherein a recessed region exists above the top surface of the at least one of the first barrier film sidewalls and in a portion of the first insulation film proximate the top surface of each said at least one of the first barrier film sidewalls.

14. The semiconductor device of claim 13 , wherein the recessed region has a width that is upwardly increasing from the top surface of the first barrier film.

15. The semiconductor device of claim 14 , wherein the via extends to completely fill the recessed region.

16. The semiconductor device of claim 11 , wherein the width of upper portion of the first lower conductor, in a direction between the first opposite lower conductor sidewall surfaces, is less than or equal to the width of the via in the first direction between opposite side surfaces at a bottom portion of the via.

17. The semiconductor device of claim 11 , further comprising:
a first upper conductor disposed directly on the via and having opposing sidewall surfaces that vertically align with respective opposing sidewall surfaces of the via.

18. The semiconductor device of claim 17 , further comprising:
a second upper conductor arranged in parallel with the first upper conductor and separated from the first upper conductor by a pitch that ranges from between about 10 nm to about 100 nm.

19. The semiconductor device of claim 11 , wherein the edge portion of the top surface of the first lower conductor is convex, and the top surface of the second lower conductor is planar.

20. A semiconductor device comprising:
a lower conductor having opposite lower conductor sidewall surfaces, and a top surface contiguous with the lower conductor sidewall surfaces, the top surface including an edge portion and a central portion;
a barrier film having barrier film sidewalls disposed directly on the lower conductor sidewall surfaces, respectively; and
a via disposed on the top surface of the lower conductor, the via having opposite via sidewall surfaces,
wherein an uppermost surface of at least one of the barrier film sidewalls is disposed at a level lower than the level of an uppermost part of the top surface of the lower conductor, and
the lower conductor has a width in a first direction at the level of said uppermost surface of at least one of the barrier film sidewalls, the via has a width in the first direction between the opposite via sidewall surfaces at a bottom portion of the via, and said width of the lower conductor is less than or equal to said width of the via.

Assignees

• Kim Dong-Kwon
• Kim Ki-Il
• Samsung Electronics Co Ltd

Inventors

• Kim Dong-Kwon
• Kim Ki-Il

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title

• H10W20/083 Primary

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title