Layout of semiconductor structure, semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-2019172831-A1
Application number	US-201715857642-A
Country	US
Kind code	A1
Filing date	Dec 29, 2017
Priority date	Dec 4, 2017
Publication date	Jun 6, 2019
Grant date	—

Abstract

A layout of semiconductor structure includes plural patterns arranged along a first direction to form plural columns, with each pattern spaced from each other. A region is defined by the patterns, and which includes a first edge and a second edge, with the first edge extended along the first direction, and the second edge extended along a second direction different from the first direction and being serrated. The second edge includes plural fragments, with each fragment being defined by at least two patterns. The present invention also provided a semiconductor device and a method of forming the same.

First claim

What is claimed is:

1 . A layout of semiconductor structure, comprising:
a plurality of patterns arranged along a first direction to form a plurality of columns, each of the patterns being spaced from each other and a region being defined by the patterns and comprising:
a first edge extended along the first direction; and
a second edge extended along a second direction different from the first direction and being serrated, wherein the second edge comprises a plurality of fragments, and each of the fragments is defined by at least two patterns.

2 . The layout of semiconductor structure according to claim 1 , wherein the two fragments adjacent to each other are extended along two different directions which are different from the first direction and the second direction, and the two different directions are across and not perpendicular to each other.

3 . The layout of semiconductor structure according to claim 1 , wherein the patterns arranged in odd columns are in alignment with each other along the second direction.

4 . The layout of semiconductor structure according to claim 1 , wherein the patterns arranged in even columns are in alignment with each other along the second direction.

5 . The layout of semiconductor structure according to claim 1 , wherein the patterns arranged in two adjacent columns are alternately arranged with each other along the second direction.

6 . The layout of semiconductor structure according to claim 1 , wherein the region further comprises a third edge extended along the second direction, and the third edge is opposite to the second edge and is serrated.

7 . The layout of semiconductor structure according to claim 6 , wherein the third edge and the second edge are asymmetric.

8 . The layout of semiconductor structure according to claim 6 , wherein the third edge and the second edge are symmetric.

9 . A semiconductor device, comprising:
a substrate, having a first region and a second region; and a material layer disposed on the substrate, the material layer comprising a plurality of patterns spaced from each other, wherein the first region is defined by the patterns, and which comprises at least two serrated edges, each of the edges comprises a plurality of fragments, and each of the fragments is defined by at least two patterns.

10 . The semiconductor device according to claim 9 , wherein the at least two serrated edges are symmetric.

11 . The semiconductor device according to claim 9 , wherein the at least two serrated edges are asymmetric.

12 . The semiconductor device according to claim 9 , wherein each of the serrated edges comprises a plurality of serrated portions, and each of the serrated portions is defined by two adjacent fragments.

13 . The semiconductor device according to claim 12 , wherein the two adjacent fragments extended along two different directions, and the two different directions are across and not perpendicular to each other.

14 . The semiconductor device according to claim 9 , wherein the patterns are arranged along a first direction to form a plurality of columns, and the patterns arranged in odd columns are in alignment with each other along a second direction different from the first direction.

15 . The semiconductor device according to claim 14 , wherein the patterns arranged in even columns are in alignment with each other along the second direction.

16 . The semiconductor device according to claim 14 , wherein the patterns arranged in two adjacent columns are alternately arranged from each other along the second direction.

17 . The semiconductor device according to claim 9 , further comprising:
a plurality of bit lines disposed on the substrate, within the first region, below the material layer; and a plurality of plugs disposed on the substrate, within the first region, the plugs and the bit lines are alternately arranged, and the patterns are disposed on the plugs.

18 . A method of forming semiconductor device, comprising:
providing a substrate, the substrate having a first region and a second region; and forming a material layer on the substrate, the material layer comprising a plurality of patterns spaced from each other, wherein the first region is defined by the patterns and which comprises at least two serrated edges, each of the edges comprises a plurality of fragments, and each of the fragments is defined by at least two patterns.

19 . The method of forming semiconductor device according to claim 18 , wherein the patterns are arranged along a first direction to form a plurality of columns, and the patterns arranged in odd columns are in alignment with each other along a second direction different from the first direction.

20 . The method of forming semiconductor device according to claim 19 , wherein the patterns arranged in two adjacent columns are alternately arranged from each other along the second direction.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Chang Feng-Yi
• Tung Yu-Cheng
• Lee Fu-Che

Classifications

• H01L27/10808

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic

• H01L27/10855 Primary

  Electricity · mapped topic

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10B12/31

  having a storage electrode stacked over the transistor · CPC title