Interconnection structure and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-10707117-B2
Application number	US-201816181817-A
Country	US
Kind code	B2
Filing date	Nov 6, 2018
Priority date	Dec 11, 2017
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

The present disclosure teaches interconnection structures and methods for manufacturing the same. In one implementation, a method may include: providing a substrate structure, including: a substrate, an interlayer dielectric layer on the substrate, a plurality of first through holes running through the interlayer dielectric layer, and a first metal layer filling the plurality of first through holes; forming a through hole structural layer on the substrate structure, where a dual-damascene through hole structure included in the through hole structural layer includes: a second through hole and a third through hole in the through hole structural layer, and an opening on the second through hole and the third through hole, and a part of the through hole structural layer between the second through hole and the third through hole is exposed in the opening; filling a second metal layer in the second through hole and the third through hole, where an upper surface of the second metal layer is lower than an upper surface of the part of the through hole structural layer; etching the part of the through hole structural layer so that the upper surface of the part is lower than the upper surface of the second metal layer; and forming, in the opening, a third metal layer connected to the second metal layer. The present disclosure addresses a problem of a cauliflower defect in the prior art.

First claim

What is claimed is:

1. A method for manufacturing an interconnection structure, comprising:
providing a substrate structure, wherein the substrate structure comprises:
a substrate,
an interlayer dielectric layer on the substrate,
a plurality of first through holes running through the interlayer dielectric layer, and
a first metal layer filling the plurality of first through holes;

forming a through hole structural layer on the substrate structure, wherein the through hole structural layer comprises a dual-damascene through hole structure, the dual-damascene through hole structure comprising:
a second through hole and a third through hole in the through hole structural layer, and
an opening on the second through hole and the third through hole,
wherein the first metal layer in one of the first through holes of the plurality of first through holes is exposed in the second through hole,
wherein the first metal layer in another one of the plurality of first through holes is exposed in the third through hole, and
wherein the second through hole, the third through hole, and a part of the through hole structural layer between the second through hole and the third through hole are exposed in the opening;

filling a second metal layer in the second through hole and the third through hole, wherein an upper surface of the second metal layer is lower than an upper surface of the part of the through hole structural layer between the second through hole and the third through hole;
etching the part of the through hole structural layer between the second through hole and the third through hole so that the upper surface of the part is lower than the upper surface of the second metal layer; and
after etching the part of the through hole structural layer, forming, in the opening, a third metal layer connected to the second metal layer.

2. The method according to claim 1 , wherein after the part of the through hole structural layer between the second through hole and the third through hole is etched, the upper surface of the part of the through hole structural layer is lower than the upper surface of the second metal layer by 50 Å to 200 Å.

3. The method according to claim 1 , wherein the part of the through hole structural layer between the second through hole and the third through hole is etched under the following process condition:
at 20-millitorr to 200-millitorr gas pressure and 100-watt to 2000-watt etching power, and with argon (Ar) as a carrier gas, where an etching process is executed by using a mixed gas of C 4 F 8 , C 4 F 6 , and O 2 .

4. The method according to claim 3 , wherein
a gas flow range of the C 4 F 8 is 10 sccm to 50 sccm;
a gas flow range of the C 4 F 6 is 10 sccm to 50 sccm;
a gas flow range of the O 2 is 2 sccm to 30 sccm; and
a gas flow range of the Ar is 100 sccm to 5000 sccm.

5. The method according to claim 1 , wherein:
the through hole structural layer comprises:
an etching stop layer on the substrate structure,
a first dielectric layer on the etching stop layer, and
a second dielectric layer on the first dielectric layer;

a dielectric constant of the first dielectric layer is lower than a dielectric constant of the second dielectric layer;
the dual-damascene through hole structure runs through the etching stop layer, the first dielectric layer, and the second dielectric layer; and
the part of the through hole structural layer between the second through hole and the third through hole exposed in the opening is a part of the first dielectric layer between the second through hole and the third through hole.

6. The method according to claim 5 , wherein a material of the first dielectric layer is a material with a low dielectric constant.

7. The method according to claim 5 , wherein the step of forming a through hole structural layer on the substrate structure comprises:
forming the etching stop layer on the substrate structure, the first dielectric layer on the etching stop layer, the second dielectric layer on the first dielectric layer, and a hard mask layer on the second dielectric layer;
etching the hard mask layer, the second dielectric layer, and the first dielectric layer to form an initial dual-damascene through hole in which a partial surface of the etching stop layer is exposed;
removing the hard mask layer after forming the initial dual-damascene through hole; and
removing the exposed part of the etching stop layer using the initial dual-damascene through hole by means of an etching process to expose the first metal layer in the first through holes, so as to form the dual-damascene through hole structure.

8. The method according to claim 1 , wherein:
materials of the first metal layer and the third metal layer comprise copper (Cu); and
a material of the second metal layer comprises cobalt.

9. The method according to claim 1 , wherein in the step of forming the through hole structural layer, the first metal layer in two adjacent first through holes in the plurality of first through holes is exposed in each of the second through hole and the third through hole.

Assignees

• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Shanghai International Corporation
• Semiconductor Mfg Beijing International Corporation

Inventors

• Han Qiuhua
• Yan Kai
• Wu Duan Yi

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title