Via formation using sidewall image transfer process to define lateral dimension

Patent metadata

Field	Value
Publication number	US-9490168-B1
Application number	US-201514710894-A
Country	US
Kind code	B1
Filing date	May 13, 2015
Priority date	May 13, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

First claim

What is claimed is:

1. A method of forming a via to an underlying layer of a semiconductor device, the method comprising the steps of:
forming a pillar over the underlying layer using a sidewall image transfer process;
forming a dielectric layer over the pillar and the underlying layer;
patterning a via mask over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar;
etching a via opening in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction; and
filling the via opening with a conductor to form the via.

2. The method of claim 1 , wherein the pillar includes a pair of pillars having a predefined spacing therebetween.

3. The method of claim 1 , wherein the pillar is adjacent to an edge of the metal layer.

4. The method of claim 1 , wherein the sidewall image transfer process includes:
forming a mandrel over the underlying layer;
depositing a spacer layer over the mandrel;
exposing an upper surface of the mandrel; and
removing the mandrel to form the pillar from the spacer layer.

5. The method of claim 4 , further comprising depositing an organic planarizing layer (OPL) after the spacer layer depositing, and wherein the exposing includes first etching the OPL and second etching the spacer layer.

6. The method of claim 4 , wherein the mandrel forming includes:
depositing a mandrel layer over the underlying layer;
patterning a mandrel mask over the mandrel layer, the mandrel mask being an inversion of the via mask; and
etching the mandrel layer using the mandrel mask to form the mandrel.

7. The method of claim 1 , wherein the filling the via opening includes depositing a liner, depositing a metal and polishing.

8. The method of claim 1 , wherein the pillar has a lateral thickness between 5 nanometers and 15 nanometers.

9. The method of claim 1 , wherein the first direction is substantially perpendicular to the second direction.

Assignees

• IBM
• Globalfoundries Inc
• St Microelectronics Inc

Inventors

• Chen Shyng-Tsong
• Chi Cheng
• Liu Chi-Chun
• Mignot Sylvie M
• Mignot Yann A
• Shobha Hosadurga K
• Spooner Terry A
• Wang Wenhui
• Xu Yongan

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title