Filling cavities in an integrated circuit and resulting devices

Patent metadata

Field	Value
Publication number	US-9524935-B2
Application number	US-201514711380-A
Country	US
Kind code	B2
Filing date	May 13, 2015
Priority date	May 13, 2015
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.

First claim

What is claimed is:

1. A method comprising:
providing active area and/or gate contacts in a first interlayer dielectric (ILD);
forming selective protective caps on upper surfaces of the contacts;
forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD;
forming a hard-mask stack on the second ILD;
forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps;
removing selective layers in the stack to decrease depths of the cavities; and
filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps,
wherein the forming of the hard-mask stack comprises:
forming a first dielectric hard-mask (DHM1) layer, a metal hard-mask (MHM) layer, a second dielectric hard-mask (DHM2) layer, a spin-on hard-mask (SOH) layer, and an antireflective coating (ARC) hard-mask layer; and
wherein the protective caps comprise ruthenium caps and the contacts are cavities filled with tungsten.

2. The method according to claim 1 , comprising performing chemical mechanical polishing (CMP) prior to forming the selective protective caps.

3. The method according to claim 1 , comprising forming an etch stop layer prior to forming the second ILD.

4. The method according to claim 1 , wherein the selective layers include the MHM layer, the DHM2 layer, the SOH layer, and the ARC layer.

5. The method according to claim 1 , further comprising:
conformally forming, prior to forming the metal layer, a barrier metal/seed layer on exposed surfaces of the DHM1 and ILD layers.

6. The method according to claim 1 , further comprising:
removing an upper portion of the one or more exposed protective caps.

7. The method according to claim 6 , wherein the MHM layer is removed at a faster rate than the upper portion of the one or more exposed protective caps.

8. The method according to claim 1 , comprising performing CMP down to an upper surface of the second ILD subsequent to filling with the metal layer.

9. The method according to claim 1 , wherein the cavities include interconnecting vias and trenches.

10. The method according to claim 1 , wherein the metal comprises copper, the method further comprising filling the cavities with the copper by electrochemical plating (ECP).

11. A method comprising:
providing active area and/or gate contacts in a first interlayer dielectric (ILD);
forming selective protective caps on upper surfaces of the contacts;
forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD;
forming a hard-mask stack on the second ILD, wherein the hard-mask includes a first dielectric hard-mask (DHM1) layer, a metal hard-mask (MHM) layer, a second DHM dielectric hard-mask (DHM2) layer, a spin-on hard-mask (SOH) layer, and an antireflective coating (ARC) hard-mask layer;
forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps;
removing selective layers in the stack to decrease depths of the cavities, wherein the selective layers include the MHM layer, the DHM2 layer, the SOH layer, and the ARC layer;
filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps; and
conformally forming, prior to forming the metal layer, a barrier metal/seed layer on exposed surfaces of the DHM1 and ILD layers,
wherein the protective caps comprise ruthenium caps, the contacts are cavities filled with tungsten.

12. The method according to claim 11 , further comprising:
removing an upper portion of the one or more exposed protective caps.

13. The method according to claim 11 , wherein the protective caps comprise ruthenium caps, the contacts are cavities filled with tungsten, and wherein the MHM layer is removed at a faster rate than the upper portion of the one or more exposed protective caps.

Assignees

• Globalfoundries Inc

Inventors

• RULLAN Jonathan Lee
• Singh Sunil Kumar

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/0698

  Local interconnections · CPC title