Estimation of effective channel length for FinFETs and nano-wires

Patent metadata

Field	Value
Publication number	US-10706209-B2
Application number	US-201916568157-A
Country	US
Kind code	B2
Filing date	Sep 11, 2019
Priority date	Sep 26, 2013
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

Roughly described, a system for estimating an effective channel length of a 3D transistor having a gate length below 20 nm involves estimating an effective volume of the channel and a cross-sectional area of the channel, and estimating the effective channel length as the ratio of effective volume to cross-sectional area. Preferably the effective volume is estimated as the sum of the Voronoi volumes within containing boundaries of the channel, excluding those volumes having a dopant concentration above the source/drain dopant concentration at the carrier injection point. The containing boundaries can be identified using geometry data describing the transistor, particularly the data identifying inner surfaces of the gate dielectric. The estimated effective channel length can be used in TCAD level analysis of the transistor and calculating characteristics of the transistor as needed for circuit simulation.

First claim

The invention claimed is:

1. A system for enhancing simulations of three-dimensional transistors, the system comprising:
a data processor;
a source of a data set for the data processor, the data set describing a dopant profile of a three-dimensional transistor having a semiconductor body, the data set also identifying a gate length for the three-dimensional transistor which is no greater than 20 nm, the data set further identifying surfaces of gate dielectric material adjacent to the semiconductor body, the data set further describing source/drain dopant concentration within each of a plurality of sub-volumes within the semiconductor body; and
a computer readable medium coupled to the data processor, the computer readable medium having stored thereon in a non-transitory manner a plurality of software code portions defining logic for:
identifying containing boundaries of a channel in dependence upon the surfaces of gate dielectric material adjacent to the semiconductor body as identified in the data set,
estimating an effective volume V and a cross-sectional area A of the three-dimensional channel of the transistor in dependence upon the dopant profile within the containing boundaries as described in the data set, including summing all of the sub-volumes which are within the containing boundaries and whose source/drain dopant concentration is below a predetermined value,
estimating an effective channel length in the three-dimensional transistor in dependence upon the effective volume V and the cross-sectional area A, and
providing the estimated effective channel length for simulation of an aspect of the three-dimensional transistor.

2. The system of claim 1 , wherein the dopant profile described by the data set indicates a continuum of source/drain dopant concentration within the semiconductor body,
and wherein estimating the effective volume in dependence upon the dopant profile comprises summing all of the sub-volumes of the semiconductor body which are within the containing boundaries and whose source/drain dopant concentration is indicated by the continuum as being below the predetermined value.

3. The system of claim 1 , wherein the predetermined value is the source/drain dopant concentration at a carrier injection point at an interface of the channel and a member of the group consisting of source and drain.

4. The system of claim 1 , wherein the source/drain dopant concentration of at least one of the sub-volumes which are within the containing boundaries, exceeds the predetermined value.

5. The system of claim 1 , wherein the software code portions for estimating a cross-sectional area A of the channel of the three-dimensional transistor, include:
choosing a particular longitudinal position along the channel; and
calculating a cross-sectional area of the channel at the particular longitudinal position in dependence upon the surfaces of the gate dielectric material identified in the data set.

6. The system of claim 5 , wherein the particular longitudinal position is the centroid of a volumetric region determined by identifying containing boundaries of the channel in dependence upon the surfaces of the gate dielectric material adjacent to the semiconductor body as identified in the data set.

7. The system of claim 1 , wherein the software code portions further define logic for:
receiving at an API input data describing aspects of the three-dimensional transistor, the data including identification of the surfaces of the gate dielectric material adjacent to the semiconductor body, and source/drain dopant concentration within each of a plurality of sub-volumes within the semiconductor body.

8. The system of claim 1 , wherein the software code portions further define logic for using the effective channel length in an analysis by simulation of an aspect of the three-dimensional transistor comprises performing analysis of the three-dimensional transistor, the analysis comprising a member of the group consisting of:
calculating an I-V profile of the three-dimensional transistor;
determining values for drain current Ids in a subthreshold region of the three-dimensional transistor;
determining electron or hole mobility in the channel of the three-dimensional transistor;
determining a saturation voltage Vdsat of the three-dimensional transistor;
determining an Early voltage of the three-dimensional transistor due to substrate current;
determining transient currents iD(t), iG(t) and iS(t) of the three-dimensional transistor; and
determining flicker noise in the three-dimensional transistor.

9. A method for enhancing simulations of three-dimensional transistors, comprising the steps of:
accessing, by a computer system, a data set describing a dopant profile of a three-dimensional transistor having a semiconductor body, the data set also identifying a gate length for the three-dimensional transistor which is no greater than 20 nm, the data set further identifying surfaces of gate dielectric material adjacent to the semiconductor body, the data set further describing source/drain dopant concentration within each of a plurality of sub-volumes within the semiconductor body;
identifying, by the computer system, containing boundaries of the channel in dependence upon the surfaces of gate dielectric material adjacent to the semiconductor body as identified in the data set;
estimating, by the computer system, an effective volume V and a cross-sectional area A of the channel of the three-dimensional transistor in dependence upon the dopant profile within the containing boundaries as described in the data set, including summing all of the sub-volumes which are within the containing boundaries and whose source/drain dopant concentration is below a predetermined value;
estimating, by the computer system, an effective channel length in the three-dimensional transistor in dependence upon the effective volume V and the cross-sectional area A; and
providing the estimated effective channel length for simulation of an aspect of the three-dimensional transistor.

10. The method of claim 9 , wherein the dopant profile described by the data set indicates a continuum of source/drain dopant concentration within the semiconductor body,
and wherein estimating the effective volume in dependence upon the dopant profile comprises summing all of the sub-volumes of the semiconductor body which are within the containing boundaries and whose source/drain dopant concentration is indicated by the continuum as being below the predetermined value.

11. The method of claim 9 , wherein the predetermined value is the source/drain dopant concentration at a carrier injection point at an interface of channel and a member of the group consisting of source and drain.

12. The method of claim 9 , wherein the source/drain dopant concentration of at least one of the sub-volumes which are within the containing boundaries, exceeds the predetermined value.

13. The method of claim 9 , wherein said estimating a cross-sectional area A of the channel of the three-dimensional ransistor, includes:
choosing a particular longitudinal position along the channel; and
calculating a cross-sectional area of the channel at the particular longitudinal position in dependence upon the surfaces of gate dielectric material identified in the data set.

14. The method of claim 9 , further comprising using the estimated effective channel length in an analysis by simulation of an aspect of the three-dimensional transistor comprises a step of performing analysis of the three-dimensional transistor which takes into account the effective volume V, the analysis comprising a member of the group c

Assignees

• Synopsys Inc

Inventors

• Moroz Victor
• Oh Yong-Seog
• Smith Stephen Lee
• Shaughnessy-Culver Michael C
• Liu Jie

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• G06F30/36 Primary

  Circuit design at the analogue level · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title