Method and apparatus for generating clock

Patent metadata

Field	Value
Publication number	US-10693472-B2
Application number	US-201916282472-A
Country	US
Kind code	B2
Filing date	Feb 22, 2019
Priority date	May 9, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A clock generation apparatus includes a pulse generator configured to generate a pulse signal and a selection signal using a reference clock signal, a delay line circuit, a switch and a controller. The delay line circuit selects, as an input signal to a delay path, the pulse signal or a fed back portion of a delay clock signal at an output of the delay path, where the selection is based on the selection signal; and thereby generates the delay clock signal. The switch switches a first voltage or a second voltage to the delay line circuit for its operation, where the first voltage further provides power to the pulse generator. The second voltage is generated based on a phase difference between the reference clock signal and the delay clock signal. The controller generates a switch control signal based on a frequency of the delay clock signal.

First claim

What is claimed is:

1. A clock generation apparatus comprising:
a pulse generator configured to generate a pulse signal and a selection signal using a reference clock signal;
a delay line circuit configured to select, as an input signal to a delay path, the pulse signal or a fed back portion of a delay clock signal at an output of the delay path, the selection being based on the selection signal, and thereby generate the delay clock signal;
a switch configured to switch, based on a switch control signal, a first voltage or a second voltage to the delay line circuit for operation thereof, wherein the first voltage further provides power to the pulse generator, and the second voltage is generated based on a phase difference between the reference clock signal and the delay clock signal; and
a controller configured to generate the switch control signal based on a frequency of the delay clock signal.

2. The clock generation apparatus of claim 1 , wherein the delay path comprises a series of delay cells,
each of the series of delay cells is configured to provide a delay varying based on a delay control signal, and
the controller is further configured to generate the delay control signal based on the frequency of the delay clock signal.

3. The clock generation apparatus of claim 2 , wherein while the first voltage is provided to the delay line circuit based on the switch control signal, the controller is configured to vary the delay control signal until a frequency error between the frequency of the delay clock signal and a target frequency falls within a pre-determined range.

4. The clock generation apparatus of claim 3 , wherein the controller is further configured to generate the switch control signal such that second voltage is provided to the delay line circuit after the frequency error falls within the pre-determined range.

5. The clock generation apparatus of claim 4 , wherein the pulse generator is further configured to generate the selection signal so that the delay line circuit selects the fed back portion of the delay clock signal after the frequency error falls within the pre-determined range.

6. The clock generation apparatus of claim 1 , wherein the pulse generator is further configured to generate the pulse signal including a first pulse synchronized to an edge of the reference clock signal, and to generate the selection signal activated during a time period that includes the first pulse.

7. The clock generation apparatus of claim 6 , wherein the pulse generator is further configured to generate the pulse signal including a second pulse synchronized to the edge of the reference clock signal, and wherein the time period during which the selection signal is activated further includes the second pulse.

8. The clock generation apparatus of claim 7 , further comprising a clock signal generator configured to generate, from the delay clock signal, an output clock signal including an edge delayed from an edge of the first pulse and a feedback clock signal including an edge delayed from an edge of the second pulse.

9. The clock generation apparatus of claim 8 , wherein the pulse generator is further configured to generate the pulse signal in which the second pulse is omitted, after the frequency of the delay clock signal equals a target frequency.

10. The clock generation apparatus of claim 8 , wherein the pulse generator is further configured to generate the pulse signal non-activated during the time period including the second pulse, after a frequency of the delay clock signal has reached a target frequency.

11. The clock generation apparatus of claim 8 , further comprising:
a frequency divider configured to divide the feedback clock signal;
a phase detector configured to detect a phase difference between the divided feedback clock signal and the reference clock signal; and
a voltage generator configured to generate the second voltage based on the detected phase difference.

12. A clock generation apparatus comprising:
a pulse generator configured to generate a pulse signal including an injection pulse synchronized to an edge of a reference clock signal;
a delay line circuit comprising a series of delay cells each providing a delay varying based on a control voltage and a delay control signal, and configured to periodically delay the injection pulse to generate a delay clock signal; and
a controller configured to:
adjust the delay control signal until a frequency error between a frequency of the delay clock signal and a target frequency falls within a predetermined range in a time period in which the control voltage is a first voltage that also provides power to the pulse generator; and
maintain the delay control signal at a last adjusted value during a time period in which the control voltage is a second voltage generated based on a phase difference between the reference clock signal and the delay clock signal, so that the frequency of the delay clock signal is further adjusted towards the target frequency.

13. The clock generation apparatus of claim 12 , further comprising a switch configured to provide the first voltage or the second voltage to the delay line circuit as the control voltage, based on a switch control signal,
wherein the controller is further configured to generate the switch control signal based on the frequency of the delay clock signal.

14. A method of generating a clock, the method comprising:
generating a pulse signal and a selection signal using a reference clock signal;
selecting one of the pulse signal and a fed back portion of a delay clock signal based on the selection signal;
generating the delay clock signal by passing the selected signal through a series of delay cells;
in a coarse tuning period, providing a first voltage, which is a constant voltage, to the series of delay cells, and adjusting a delay of the series of delay cells until a frequency error between a frequency of the delay clock signal and a target frequency falls within a pre-determined range;
in a fine tuning period, generating a second voltage based on a phase difference between the reference clock signal and the delay clock signal, and providing the second voltage to the series of delay cells.

15. The method of claim 14 , wherein the first voltage is also a voltage for providing power when generating the pulse signal and the selection signal.

16. The method of claim 14 , wherein the generating of the pulse signal and the selection signal comprises:
generating, in the coarse tuning period, the pulse signal including a first pulse and a second pulse each synchronized to an edge of the reference clock signal; and
generating, in the coarse tuning period, the selection signal activated in a period including the first pulse and the second pulse.

17. The method of claim 16 , wherein the generating of the pulse signal and the selection signal further comprises generating the pulse signal and the selection signal such that a period in which the selection signal is activated includes only the first pulse, after the fine tuning period has ended.

18. The method of claim 16 , further comprising:
generating, from the delay clock signal, an output clock signal including an edge delayed from an edge of the first pulse; and
generating, from the delay clock signal, a feedback clock signal including an edge delayed from an edge of the second pulse.

19. The method of claim 18 , wherein the generating of the second voltage comprises:
dividing the feedback clock signal;
detecting a phase difference between the divided feedback clo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seung-Jin
• Lee Jong-Woo
• Jo Min-Gyu
• Han Byung-Ki

Classifications

• H03L7/0818 Primary

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H03L7/0998

  using phase interpolation · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/089 Primary

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title