Digital fractional-N multiplying injection locked oscillator

Patent metadata

Field	Value
Publication number	US-9614537-B1
Application number	US-201615093655-A
Country	US
Kind code	B1
Filing date	Apr 7, 2016
Priority date	Apr 7, 2016
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses. The clock generator circuit includes a phase detector configured to compare the output clock and the reference clock and generate the phase error signal, and a control circuit configured to generate the first and second control codes based on the phase error signal.

First claim

What is claimed is:

1. A clock generator circuit, comprising:
a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock;
a digitally controlled delay line (DCDL) configured to delay the reference clock based on a first control code;
a pulse generator configured to generate pulses based on the delayed reference clock;
a digitally controlled oscillator (DCO) including an injection input coupled to the pulse generator to receive the pulses, the DCO configured to generate an output clock based on the pulses and a second control code;
a phase detector configured to compare phases of the output clock and the reference clock and generate the phase error signal; and
a control circuit configured to generate the first and second control codes based on the phase error signal.

2. The clock generator circuit of claim 1 , wherein the control circuit is further configured to control the pulse generator to periodically gate the pulses at a gating rate.

3. The clock generator circuit of claim 1 , wherein the DCDL is a first DCDL and wherein the fractional reference generator comprises:
at least one delta-sigma modulator configured to generate at least one control signal based on a third control code;
a second DCDL configured to delay the base reference clock to generate the reference clock; and
a calibration circuit configured to adjust the delay of the second DCDL based on the at least one control signal and the phase error signal.

4. The clock generator of claim 1 , wherein the rational multiple is a non-integer multiple.

5. The clock generator of claim 1 , wherein the control circuit comprises:
a first digital accumulator configured to generate the first control code based on the phase error signal; and
a second digital accumulator configured to generate the second control code based on the phase error signal.

6. The clock generator of claim 5 , wherein the control circuit further comprises:
a gate control circuit configured to generate a gate control signal, the gate control signal being coupled to the pulse generator; and
a de-multiplexer configured to selectively couple the phase error signal to either the first digital accumulator or the second digital accumulator based on the gate control signal.

7. The clock generator of claim 1 , further comprising:
a multiplexer configured to select either an external reference clock or an internal reference clock as the base reference clock based on a select signal.

8. A clock generator circuit, comprising:
a fractional reference generator having a first input configured to receive a base reference clock, a second input configured to receive a frequency control code, a third input, and an output configured to provide a reference clock;
a digitally controlled delay line (DCDL) having a first input coupled to the output of the fractional reference generator, a second input, and an output;
a pulse generator having a first input coupled to the output of the DCDL, a second input, and an output;
a digitally controlled oscillator (DCO) having a first input coupled to the output of the pulse generator, a second input, and an output configured to provide an output clock;
a phase detector having a first input coupled to the output of the DCO, a second input coupled to the output of the fractional reference generator, and an output coupled to the third input of the reference frequency generator; and
a control circuit having a first input coupled to the output of the phase detector, a first output coupled to the second input of the DCDL, a second output coupled to the second input of the pulse generator, and a third output coupled to the second input of the DCO.

9. The clock generator circuit of claim 8 , wherein the DCDL is a first DCDL, and wherein fractional reference generator comprises:
at least one delta-sigma modulator each having an input and output, the input of each delta-sigma modulator being the second input of the fractional reference generator;
a calibration circuit having a first input coupled to the output of each delta-sigma modulator, a second input, and an output, the second input of the calibration circuit being the third input of the fractional reference generator; and
a second DCDL having a first input, a second input coupled to the output of the calibration circuit, and an output, the first input of the second DCDL being the first input of the fractional reference generator and the output of the second DCDL being the output of the fractional reference generator.

10. The clock generator circuit of claim 8 , wherein the control circuit comprises:
a first digital accumulator having an input and an output, the output of the first digital accumulator being the first output of the control circuit; and
a second digital accumulator having an input and an output, the output of the second digital accumulator being the third output of the control circuit.

11. The clock generator of claim 10 , wherein the control circuit further comprises:
a gate control circuit having an output being the second output of the control circuit.

12. The clock generator circuit of claim 11 , wherein the control circuit further comprises:
a de-multiplexer having a first input coupled to the output of the phase detector, a second input coupled to the output of the gate control circuit, a first output coupled to the input of the first digital accumulator, and a second output coupled to the input of the second digital accumulator.

13. The clock generator circuit of claim 8 , further comprising:
a multiplexer having a first input configured to receive an external reference clock, a second input configured to receive an internal reference clock, a third input configured to receive a select signal, and an output coupled to the first input of the fractional reference generator to provide the base reference clock.

14. The clock generator of claim 8 , wherein the phase detector comprises a sub-sampling bang-bang phase detector.

15. A method of generating an output clock, comprising:
generating a reference clock in response to a base reference clock and a phase error, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock;
delaying the reference clock based on a first control code;
generating pulses based on the delayed reference clock;
generating the output clock based on a second control code and the pulses;
comparing phases of the output clock and the reference clock and generate the phase error signal; and
generating the first and second control codes based on the phase error signal.

16. The method of claim 15 , further comprising:
periodically gating the pulses at a gating rate.

17. The method of 15 , wherein the step of generating the reference clock comprises:
generating at least one control signal using at least one delta-sigma modulator based on a third control code;
delaying the base reference clock to generate the reference clock; and
adjusting the delay of the second DCDL based on the at least one control signal and the phase error signal.

18. The method of claim 15 , wherein the step of generating the first and second control codes comprises:
generating the first control code based on the phase error signal; and
generating the second control code based on the phase error signal.

19. The method of claim 18 , wherein step of

Assignees

• Xilinx Inc

Inventors

• Nandwana Romesh Kumar
• Upadhyaya Parag

Classifications

• H03L7/24 Primary

  using a reference signal directly applied to the generator · CPC title

• H03L7/081

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L7/0805 Primary

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title