Multiplying delay-locked loop using sampling time-to-digital converter

Patent metadata

Field	Value
Publication number	US-2017366191-A1
Application number	US-201715629427-A
Country	US
Kind code	A1
Filing date	Jun 21, 2017
Priority date	Jun 21, 2016
Publication date	Dec 21, 2017
Grant date	—

Abstract

A multiplying delay-locked loop circuit includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits. The circuitry for deriving a digital control signal includes a sampling time-to-digital converter (STDC) configured to operate on a time delay between inputs to generate the digital control signal. The STDC subtracts a second difference the signals derived from the delay chain output and output of the feedback divider from a first difference between the signals derived from the delay chain output and output of the feedback divider to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.

First claim

What is claimed is:

1 . A multiplying delay-locked loop circuit, comprising:
a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output; and a feedback loop including circuitry for deriving, from feedback signals supplied by the delay chain, a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits in the plurality of variable delay circuits.

2 . The multiplying delay-locked loop circuit of claim 1 , wherein the feedback loop further comprises a feedback divider for dividing the delay chain output that is fed back for comparison to a reference signal, thereby multiplying output of the multiplying delay-locked loop circuit.

3 . The multiplying delay-locked loop circuit of claim 2 , wherein the circuitry for deriving a digital control signal comprises a sampling time-to-digital converter configured to operate on a time delay between inputs, including signals derived from the delay chain output and output of the feedback divider, to generate the digital control signal as an output.

4 . The multiplying delay-locked loop circuit of claim 3 , wherein:
the sampling time-to-digital converter subtracts a second difference between the one of the signals derived from the delay chain output and output of the feedback divider and the another of the signals derived from the delay chain output and output of the feedback divider, from a first difference between the one of the signals derived from the delay chain output and output of the feedback divider and the another of the signals derived from the delay chain output and output of the feedback divider, to provide a difference value; and the difference value indicates sign and magnitude of output offset in the delay chain output.

5 . The multiplying delay-locked loop circuit of claim 3 , wherein the feedback loop further comprises an edge generator circuit that derives the signals derived from the delay chain output and output of the feedback divider.

6 . The multiplying delay-locked loop circuit of claim 5 , wherein the edge generator circuit comprises:
a plurality of flip-flops clocked by the delay chain output; wherein: the plurality of flip-flops includes a first chain of flip-flops; the output of the feedback divider is input to the first chain of flip-flops; one of the signals derived from the delay chain output and the output of the feedback divider is an output of a final flip-flop in the first chain of flip-flops; and another of the signals derived from the delay chain output and the output of the feedback divider is a delayed output of an intermediate flip-flop in the first chain of flip-flops.

7 . The multiplying delay-locked loop circuit of claim 6 , wherein:
the plurality of flip-flops includes a second chain of flip-flops; the output of the feedback divider is input also to the second chain of flip-flops; the first difference is taken on a rising edge of output of the second chain of flip-flops; and the second difference is taken on a falling edge of the output of the second chain of flip-flops.

8 . The multiplying delay-locked loop circuit of claim 7 , wherein:
the first chain of flip-flops includes three flip-flops; and the second chain of flip-flops includes two flip-flops.

9 . The multiplying delay-locked loop circuit of claim 8 , wherein the intermediate flip-flop in the first chain of flip-flops is the second flip-flop in the first chain of flip-flops.

10 . The multiplying delay-locked loop circuit of claim 6 , wherein the first chain of flip-flops includes three flip-flops.

11 . The multiplying delay-locked loop circuit of claim 10 , wherein the intermediate flip-flop in the first chain of flip-flops is the second flip-flop in the first chain of flip-flops.

12 . The multiplying delay-locked loop circuit of claim 5 , wherein:
the delay chain includes an input multiplexer having, as a first multiplexer input, the delay chain output and, as a second multiplexer input, a reference signal; output of the input multiplexer is an input to the edge generator circuit; and the multiplying delay-locked loop circuit further comprises selection logic that controls output of the input multiplexer based on the output of the feedback divider and the output of the input multiplexer.

13 . A wireless transceiver including the multiplying delay-locked loop circuit of claim 1 .

14 . A method of controlling a multiplying delay-locked loop circuit, the multiplying delay-locked loop circuit including a delay chain and having a delay chain output, and a feedback loop including a feedback divider for dividing the delay chain output, the method comprising:
inputting, to a sampling time-to-digital converter, signals derived from (a) an output of a delay chain having a plurality of variable delay circuits that are connected in series and fed back in a feedback loop to input of the delay chain, and (b) an output of a feedback divider in the feedback loop, the feedback divider being configured to divide the delay chain output thereby multiplying output of the delay-locked loop circuit; and inputting an output signal of the sampling time-to-digital converter as a control signal to ones of the variable delay circuits in the plurality of variable delay circuits.

15 . The method of claim 14 , further comprising using an edge generator to derive the signals derived from the delay chain output and output of the feedback divider for input to the sampling time-to-digital converter.

16 . The method of claim 15 , wherein using the edge generator comprises:
inputting the output of the feedback divider to a first chain of flip-flops; using an output of a final flip-flop in the first chain of flip-flops as one of the signals derived from the delay chain output and the output of the feedback divider; and using an output of an intermediate flip-flop in the first chain of flip-flops as another of the signals derived from the delay chain output and the output of the feedback divider.

17 . The method of claim 16 , further comprising using the sampling time-to-digital converter to subtract a second difference between the one of the signals derived from the delay chain output and output of the feedback divider and the another of the signals derived from the delay chain output and output of the feedback divider, from a first difference between the one of the signals derived from the delay chain output and output of the feedback divider and the another of the signals derived from the delay chain output and output of the feedback divider, to provide a difference value that indicates sign and magnitude of output offset in the delay chain output.

18 . The method of claim 17 , further comprising:
inputting the output of the feedback divider also to a second chain of flip-flops; taking the first difference on a rising edge of output of the second chain of flip-flops; and taking the second difference on a falling edge of the output of the second chain of flip-flops.

19 . The method of claim 15 , further comprising selecting between a reference signal and the delay chain output as an input to the edge generator.

20 . The method of claim 19 wherein the selecting is based on the delay chain output and the output of the feedback divider.

Assignees

• Marvell World Trade Ltd

Inventors

• Wang Haisong
• Burg Olivier

Classifications

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0818 Primary

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title