Gain calibration for direct modulation synthesizer using a look-up table searched by a reduced count from an overflow counter

Patent metadata

Field	Value
Publication number	US-9935640-B1
Application number	US-201715427312-A
Country	US
Kind code	B1
Filing date	Feb 8, 2017
Priority date	Feb 8, 2017
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A two-point modulation Phase-Locked Loop (PLL) has a gain-adjustable voltage-controlled oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to a Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. A calibration unit divides the VCO output and counts pulses. During calibration, the data modulation signal is set to minimum and then maximum values and VCO output pulses counted. A count difference for the data modulation signal at maximum and minimum values is input to a Look-Up Table (LUT) to read out a gain calibration value. During normal operation mode, the gain calibration value from the LUT is applied to a second input of the DAC, which drives the VCO to adjust VCO gain. A switch before the VCO opens the loop for faster open-loop calibration.

First claim

We claim:

1. An adjustable-gain synthesizer comprising:
a phase detector that compares a reference clock to a feedback clock;
a charge pump activated by the phase detector;
a loop filter that is charged and discharged by the charge pump;
a voltage-controlled oscillator (VCO) having a VCO voltage input that determines a frequency of a VCO output, and a gain-adjusting input that adjusts a VCO gain and modulates the frequency of the VCO output;
a switch that connects the loop filter to the VCO voltage input during a normal mode, and disconnects the loop filter and applies a reference voltage to the VCO voltage input during a calibration mode, wherein the adjustable-gain synthesizer operates in open-loop mode during the calibration mode;
a feedback divider that divides the VCO output by a divisor to generate the feedback clock;
a calibration unit having a pulse counter that receives the VCO output and generates a pulse count for a time period;
a Digital-to-Analog Converter (DAC) that receives a modulation input and a gain-calibration input, the modulation input receiving a data modulation signal, the DAC generating a signal to the gain-adjusting input of the VCO;
a Look-Up Table that is addressed by a pulse-count difference to output a DAC reference value to apply to the gain-calibration input of the DAC; and
a controller in the calibration unit that forces the data modulation signal to a maximum value while the pulse counter generates a first pulse count for a time period;
the controller forcing the data modulation signal to a minimum value while the pulse counter generates a second pulse count for the time period;
the controller sending the pulse-count difference to the Look-Up Table, wherein the pulse-count difference is generated as a difference of the first and second pulse counts;
wherein the DAC reference value is applied to the DAC during the normal mode to adjust the gain-adjusting input of the VCO and perform gain compensation,
whereby calibration determines the pulse-count difference which looks up the DAC reference value in the Look-Up Table to adjust the VCO gain of the VCO.

2. The adjustable-gain synthesizer of claim 1 wherein the Look-Up Table has rows that are addressed by the pulse-count difference, the rows each storing a DAC reference value for output;
wherein division and multiplication are not performed by the calibration unit during calibration but are pre-computed into the Look-Up Table.

3. The adjustable-gain synthesizer of claim 2 wherein the Look-Up Table comprises pre-computed values of the DAC reference value as a function of the pulse-count difference, wherein the DAC reference value is:
SFD/[[( Fref×K/N times)×(Count Mod 1−Count Mod 2)]/( DACREF initial)];

wherein SFD is a specified frequency deviation in Hertz;
Fref is a reference frequency of the reference clock in Hertz;
Ntimes is a number of cycles of Fref;
Count Mod 1−Count Mod 2 is the pulse-count difference;
DACREFinitial is an initial value of the DAC reference value; and
K is a divisor for the pulse counter that is 1 or more.

4. The adjustable-gain synthesizer of claim 3 wherein the controller applies the initial value of the DAC reference value to the DAC during calibration.

5. The adjustable-gain synthesizer of claim 4 wherein the initial value of the DAC reference value is half of a range of possible values of the DAC reference value.

6. The adjustable-gain synthesizer of claim 5 wherein the data modulation signal has at least 8 binary bits.

7. The adjustable-gain synthesizer of claim 5 wherein the DAC reference value is a binary word having at least 7 bits.

8. The adjustable-gain synthesizer of claim 3 wherein the pulse counter is an overflow counter that directly generates the pulse count difference by modifying the first pulse count as the second pulse count is being generated.

9. The adjustable-gain synthesizer of claim 3 wherein the pulse counter comprises:
a divided pulse counter;
a pre-divider that generates a pulse to the divided pulse counter after every K pulses of the VCO output, wherein K is a real number of at least 1;
whereby the VCO output is divided by K before counting.

10. The adjustable-gain synthesizer of claim 3 wherein the feedback divider is a multi-mode divider allowing for fractional divisors.

11. The adjustable-gain synthesizer of claim 10 further comprising:
a sigma-delta modulator, coupled to the feedback divider, for dithering two or more integer divisors to apply to the feedback divider.

12. The adjustable-gain synthesizer of claim 11 further comprising:
a summer, receiving the data modulation signal and a channel select signal, for generating a modulating signal to the sigma-delta modulator;
wherein data modulation is injected at the feedback divider and at the gain-adjusting input of the VCO,
wherein the adjustable-gain synthesizer is a two-point modulation Phase-Locked Loop (PLL).

13. A two-point modulation Phase-Locked Loop (PLL) comprising:
a voltage-controlled oscillator (VCO) that generates a VCO output having a frequency determined by a VCO analog input and a gain modulation input;
a feedback divider that generates a feedback clock by dividing the VCO output by a divisor, wherein the divisor is modulated by a modulating data input;
a phase comparator that compares the feedback clock to a reference clock to generate a phase-compare result;
a loop filter generating a loop voltage;
a charge pump that charges and discharges the loop filter in response to the phase-compare result;
a switch that connects the loop voltage to the VCO analog input during a normal mode of operation, and connects a reference voltage to the VCO analog input during a calibration mode;
a clock counter that receives the VCO output and generates a count difference value;
a Digital-to-Analog Converter (DAC) that receives the modulating data input and a calibration input and generates an analog voltage to the gain modulation input of the VCO;
a Look-Up Table storing calibration values that are applied to the calibration input of the DAC in response to the count difference value; and
a state machine that forces the modulating data input to a minimum state for a first measurement period of time and to a maximum state for a second measurement period of time;
wherein the clock counter counts pulses of the VCO output during the first and second measurement periods of time and generates the count difference value as a difference in a first count during the first measurement period of time and a second count during the second measurement period of time;
wherein the count difference value is applied to the Look-Up Table to read a calibration value that is applied to the calibration input of the DAC during the normal mode to compensate the VCO.

14. The two-point modulation PLL of claim 13 wherein the clock counter further comprises:
a fast divider that receives the VCO output and generates a divided signal having a reduced frequency than the VCO output; and
a divided clock counter that counts the divided signal from the fast divider to generate a measured count value.

15. The two-point modulation PLL of claim 14 wherein the Look-Up Table has rows that are addressed by the count difference value, the rows each storing a DAC reference value for output;
wherein division and multiplication are not performed during calibration but are pre-computed into the Look-Up Table.

16. The two-point modulation PLL of claim 14 wherein the Look-Up Table comprises pre-computed values of the calibration values as a function of the count difference value

Assignees

• Hong Kong Applied Science & Tech Research Inst Co Ltd

Inventors

• Chan Tat Fu
• Zheng Shiyuan
• Li Yunlong
• Cheng Wang Chi

Classifications

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/1974 Primary

  for fractional frequency division · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03C3/0958

  applying frequency modulation by varying the characteristics of the voltage controlled oscillator · CPC title