Integrated circuit including parametric analog elements

Patent metadata

Field	Value
Publication number	US-9858367-B1
Application number	US-87299510-A
Country	US
Kind code	B1
Filing date	Aug 31, 2010
Priority date	Aug 31, 2009
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A parameterizable integrated circuit (IC) and method for designing, refining and implementing a circuit including the parameterizable IC are described. The method begins with receiving information on candidate sensing sub-circuits, parameterizable ICs and user specified requirements for the circuit including physical properties to be sensed and target values for the circuit. Each of the parameterizable ICs include a number of parametric analog and digital circuit elements, and a scheduler to schedule resources of the IC according to measurement priorities, measurement rates and the available circuit elements. Next, each of the candidate sensor-sub-circuits is evaluated with reference to the specified requirements, and each of the candidate ICs evaluated with reference to the requirements and the sensor-sub-circuits. Generally, the method further includes communicating to a user a number of candidate circuit-designs within a predetermined percentage of the one or more target values for the circuit.

First claim

What is claimed is:

1. A parameterizable Integrated Circuit (IC) comprising:
a number of parametric sensing signal chains, each including analog and digital circuit elements;
a number of input pins to the sensing signal chains, each of the input pins electrically coupled to one or more external sensing elements for measurement of physical properties for which sensing elements exist; and
a scheduler to schedule and allocate the analog and digital circuit elements to each of the parametric sensing signal chains, based on measurement priorities, and measurement rates,
wherein the scheduler operates autonomously to implement changes in a time for which the analog and digital circuit elements are allocated to each of the parametric sensing signal chains based on a result of the measurement of physical properties.

2. The parameterizable IC according to claim 1 , wherein the scheduler implements changes the time based on user specified targets in measurement rate or accuracy.

3. The parameterizable IC according to claim 1 , wherein the one or more external sensing elements comprise sensors to sense pressure, temperature, weight, humidity, air-flow, acceleration, tilt, rotation, position, light, gas, liquid-level, touch and proximity sensing.

4. The parameterizable IC according to claim 1 , wherein the analog and digital circuits elements comprise one or more analog multiplexers, analog gain blocks, analog common mode shifting blocks, analog and digital noise suppression blocks, analog-to-digital converters, digital averaging and filtering circuits, gain adjustment circuits, linearity adjustment circuits and temperature compensation circuits.

5. The parameterizable IC according to claim 1 , wherein the number of parametric sensing signal chains include at least two parametric sensing signal chains that share at least one analog or digital circuit element.

6. The parameterizable IC according to claim 5 , wherein the at least one analog or digital circuit element comprises an analog-to-digital converter, and wherein the scheduler operates autonomously to change the time or order in which the analog-to-digital converter is allocated to the two of the plurality parametric sensing signal chains.

7. A parameterizable Integrated Circuit (IC) comprising:
resources including analog and digital elements and sub-circuits;
a plurality of parametric sensing signal chains, each including a number of the resources, and wherein at least two of the plurality parametric sensing signal chains share at least one resource;
a number of input pins each electrically coupled to an external sensing element for sensing physical properties external to the parameterizable IC, and to the plurality of parametric sensing signal chains to provide signals from said external sensing element to the parametric sensing signal chains for measurement of said physical properties; and
a scheduler to schedule and allocate resources to each of the parametric sensing signal chains,
wherein the scheduler operates autonomously to schedule and allocate resources to each of the parametric sensing signal chains at repeated time intervals, and to implement changes in a time or order of the allocation of resources based on user specified targets, a result of the measurement of physical properties and the analog and digital elements and sub-circuits available.

8. The parameterizable IC according to claim 7 , wherein the user specified targets include measurement rate and measurement accuracy.

9. The parameterizable IC according to claim 7 , wherein the external sensing element comprises a sensor to sense pressure, temperature, weight, humidity, air-flow, acceleration, tilt, rotation, position, light, gas, liquid-level, touch or proximity sensing.

10. The parameterizable IC according to claim 7 , wherein the resources comprise one or more analog multiplexers, analog gain blocks, analog common mode shifting blocks, analog and digital noise suppression blocks, analog-to-digital converters, digital averaging and filtering circuits, gain adjustment circuits, linearity adjustment circuits and temperature compensation circuits.

11. The parameterizable IC according to claim 7 , wherein the at least one resource shared by at least two of the plurality parametric sensing signal chains comprises an analog-to-digital converter, and wherein the scheduler operates autonomously to change the time or order in which the analog-to-digital converter is allocated to the two of the plurality parametric sensing signal chains.

12. A parameterizable-Integrated Circuit (IC) comprising:
parametric sensing signal chains, each including a number of analog and digital circuit elements, and at least two parametric sensing signal chains sharing at least one of the number of analog and digital circuit elements;
input pins each electrically coupled to an external sensing element for sensing physical properties external to the parameterizable IC, and to the parametric sensing signal chains to provide signals for measurement of said physical properties to the parametric sensing signal chains; and
a scheduler to schedule and allocate the number of analog and digital circuit elements to each of the parametric sensing signal chains,
wherein the scheduler operates autonomously to implement changes in a time for which the number of analog and digital circuit elements are allocated to each of the parametric sensing signal chains based on a result of the measurement of said physical properties.

13. The parameterizable IC according to claim 12 , wherein the at least one analog or digital circuit element shared by the two parametric sensing signal chains comprises an analog-to-digital converter, and wherein the scheduler operates autonomously to change in the time or order in which the analog-to-digital converter is allocated to the two parametric sensing signal chains.

14. The parameterizable IC according to claim 13 , wherein the analog and digital circuits elements comprise one or more analog multiplexers, analog gain blocks, analog common mode shifting blocks, analog and digital noise suppression blocks, analog-to-digital converters, digital averaging and filtering circuits, gain adjustment circuits, linearity adjustment circuits and temperature compensation circuits.

15. The parameterizable IC according to claim 12 , wherein the external sensing element comprises a sensor to sense pressure, temperature, weight, humidity, air-flow, acceleration, tilt, rotation, position, light, gas, liquid-level, touch or proximity sensing.

Assignees

• Visconti Antonio
• Lehoty David
• Cypress Semiconductor Corp

Inventors

• Visconti Antonio
• Lehoty David

Classifications

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/36 Primary

  Circuit design at the analogue level · CPC title