Method, apparatus, computer device, and storage medium for automatic design of analog circuits based on tree structure
US-2022414307-A1 · Dec 29, 2022 · US
Circuit design at the mixed level of analogue and digital signals
Circuit design at the mixed level of analogue and digital signals · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F30/38 |
| Official title | Circuit design at the mixed level of analogue and digital signals |
| Display label | Circuit design at the mixed level of analogue and digital signals |
| Total patents | 131 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 6 |
| 2016 | 3 |
| 2017 | 6 |
| 2018 | 3 |
| 2019 | 2 |
| 2020 | 9 |
| 2021 | 29 |
| 2022 | 16 |
| 2023 | 25 |
| 2024 | 13 |
| 2025 | 15 |
| 2026 | 4 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Horizontal and vertical assertions for validation of neuromorphic hardware
US-2022129742-A1 · Apr 28, 2022 · US
Automated analog and mixed-signal circuit design and validation
US-2021390243-A1 · Dec 16, 2021 · US
Multi-algorithmic approach to represent highly non-linear high dimensional space
US-2021390234-A1 · Dec 16, 2021 · US
Programmatic circuit partitioning and topology identification
US-2021390239-A1 · Dec 16, 2021 · US
Automated geometry optimization for analog, mixed-signal circuit design
US-2021390233-A1 · Dec 16, 2021 · US
Automated analog and mixed-signal circuit design and validation
US-2021390232-A1 · Dec 16, 2021 · US
Process aware compact representation of integrated circuits
US-2021390237-A1 · Dec 16, 2021 · US
Guiding sample size choice in analog defect or fault simulation
US-2021383047-A1 · Dec 9, 2021 · US
Finding equivalent classes of hard defects in stacked mosfet arrays
US-2021374313-A1 · Dec 2, 2021 · US
Defect weigh formulas for analog defect simulation
US-2021350058-A1 · Nov 11, 2021 · US
Simulation method for use in functional equivalence check
US-11170147-B2 · Nov 9, 2021 · US
Method implemented on computer system executing instructions for semiconductor design simulation
US-11144699-B2 · Oct 12, 2021 · US
System for facilitating secure communication in system-on-chips
US-2021312115-A1 · Oct 7, 2021 · US
Method for finding equivalent classes of hard defects in stacked mosfet arrays
US-2021312113-A1 · Oct 7, 2021 · US
Recording medium, computing method, and computing device
US-2021294952-A1 · Sep 23, 2021 · US
Integrated circuit with a dynamics-based reconfigurable logic block
US-2021294954-A1 · Sep 23, 2021 · US
Recording medium, computing method, and computing device
US-2021294956-A1 · Sep 23, 2021 · US
Tools and methods for designing a circuit, and circuits made thereby
US-11126772-B1 · Sep 21, 2021 · US
Neuromorphic memories with split gate flash multi-level cell and method of making the same
US-11119917-B2 · Sep 14, 2021 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F30/38?
- CPC G06F30/38 is the Cooperative Patent Classification code for “Circuit design at the mixed level of analogue and digital signals.”
- How many patents are filed under CPC G06F30/38 (Circuit design at the mixed level of analogue and digital signals)?
- Our database includes 131 publications tagged with this CPC code.
- Is patent activity under CPC G06F30/38 growing?
- Publication counts under this code: 13 in 2024 vs 15 in 2025 (latest complete years).