Mixed signal TDC with embedded T2V ADC

Patent metadata

Field	Value
Publication number	US-8957712-B2
Application number	US-201313842481-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.

First claim

What is claimed is:

1. A time-to-digital converter comprising:
an edge detector responsive to first and second signals, said second signal comprising a plurality of edges during each period of the first signal, said edge detector adapted to detect, during each period of the first signal, an edge of the second signal that is closest to an edge of the first signal;
a time-to-voltage converter adapted to generate a voltage proportional to a difference in time between the detected edge of the second signal and the edge of the first signal, wherein the time-to-digital converter has first and second differential outputs adapted to be charged to a predefined voltage level in response to a reset signal, wherein a first conductive path is formed between the first differential output and a first supply voltage in response to the edge of the first signal during a first time period, and wherein a second conductive path is formed between the second differential output and the first supply voltage in response to the detected edge of the second signal during a second time period, said first and second time periods not to overlap; and
an analog-to-digital converter adapted to digitize a difference in voltages of the first and second differential outputs.

2. The time-to-digital converter of claim 1 wherein said time-to-voltage converter further comprises:
first and second transistors adapted to provide the first conductive path between the first differential output and the first supply voltage; and
third and fourth transistors adapted to provide the second conductive path between the second differential output and the first supply voltage.

3. The time-to-digital converter of claim 2 wherein said time-to-voltage converter further comprises:
a fifth transistor adapted to charge the first differential output to the predefined voltage level; and
a sixth transistor adapted to charge the second differential output to the predefined voltage level, wherein the predefined voltage level is a second supply voltage.

4. The time-to-digital converter of claim 3 wherein said fifth and sixth transistors are NMOS transistors and wherein the second supply voltage is smaller than the first supply voltage.

5. The time-to-digital converter of claim 4 further comprising:
a first plurality of capacitors each adapted to be coupled between the first differential output and the second supply voltage in response to a different one of a first plurality of signals; and
a second plurality of capacitors each adapted to be coupled between the second differential output and the second supply voltage in response to a different one of a second plurality of signals.

6. The time-to-digital converter of claim 5 wherein the analog-to-digital converter is a successive approximation register (SAR) analog-to-digital converter, and wherein the first and second plurality of capacitors perform sample and hold operations for the analog-to-digital converter.

7. The time-to-digital converter of claim 6 wherein said analog-to-digital converter further comprises a control logic adapted to generate the first and second plurality of signals.

8. The time-to-digital converter of claim 7 wherein said analog-to-digital converter further comprises a comparator adapted to compare voltages of the first and second differential outputs of the time-to-voltage converter and supply a comparison signal to the control logic.

9. The time-to-digital converter of claim 8 wherein said edge detector comprises a plurality of buffers and variable capacitors, wherein the delay across each of a subset of the plurality of buffers is adjusted to a predefined fraction of a period of the second signal by varying the capacitances of a subset of the plurality of variable capacitors.

10. The time-to-digital converter of claim 8 wherein said edge detector further comprises a plurality of flip-flops having a plurality of clock input terminals driven by a plurality of output signals of the plurality of buffers.

11. A method of converting a difference between transition times of a first signal and a second signal to a digital signal, said second signal comprising a plurality of transitions during each period of the first signal, the method comprising:
detecting, during each period of the first signal, a transition of the second signal closest in time to a transition of the first signal;
charging first and second differential outputs to a first supply voltage;
forming a first conductive path between the first differential output and a second supply voltage in response to the transition of the first signal during a first time period;
forming a second conductive path between the second differential output and the second supply voltage in response to the detected transition of the second signal during a second time period, said first and second time periods not to overlap;
generating a voltage proportional to a difference in time between the detected transition of the second signal and the transition of the first signal; and
digitizing the voltage.

12. The method of claim 11 further comprising:
forming the first conductive path via first and second transistors; and
forming the second conductive path via third and fourth transistors.

13. The method of claim 12 further comprising:
charging the first differential output to the first supply voltage via a fifth transistor; and
charging the second differential output to the first supply voltage via a sixth transistor.

14. The method of claim 13 wherein said fifth and sixth transistors are NMOS transistors and wherein the second supply voltage is greater than the first supply voltage.

15. The method of claim 14 further comprising:
forming a first plurality of capacitors each adapted to be coupled between the first differential output and the second supply voltage in response to a different one of a first plurality of signals; and
forming a second plurality of capacitors each adapted to be coupled between the second differential output and the second supply voltage in response to a different one of a second plurality of signals.

16. The method of claim 15 further comprising:
digitizing the difference in voltages of the first and second differential outputs using a successive approximation register (SAR) analog-to-digital converter; and
performing sample and hold operations using the first and second plurality of capacitors.

17. The method of claim 16 further comprising:
generating the first and second plurality of signals using a control logic disposed in the SAR analog-to-digital converter.

18. The method of claim 17 further comprising:
comparing voltages of the first and second differential outputs to generate a comparison signal; and
delivering the comparison signal to the control logic.

19. The method of claim 18 further comprising:
forming a plurality of buffers in series;
disposing a plurality of variable capacitors at outputs of the plurality of buffers;
applying the first signal to an input of a first one of the plurality of buffers; and
varying capacitances of the plurality of variable capacitors such that a delay across each of a subset of the plurality of buffers is adjusted to a predefined fraction of a period of the second signal.

20. The method of claim 19 further comprising:
detecting the transition of the second signal closest in time to the transition of the first signal by using a plurality of flip-flops having a plurality of clock input terminals driven by a plurality of output signals of the plural

Assignees

• Qualcomm Inc

Inventors

• Tang Yi
• Sun Bo

Classifications

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03M1/50 Primary

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title