Three-dimensional memory device having semiconductor plug formed using backside substrate thinning

Patent metadata

Field	Value
Publication number	US-10679985-B2
Application number	US-201816194309-A
Country	US
Kind code	B2
Filing date	Nov 17, 2018
Priority date	Oct 23, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers;
a channel structure extending vertically through the memory stack and comprising:
a channel plug in a lower portion of the channel structure;
a memory film along a sidewall of the channel structure; and
a semiconductor channel over the memory film and in contact with the channel plug; and

a semiconductor layer above the memory stack and comprising a semiconductor plug above and in contact with the semiconductor channel, wherein a top surface of the semiconductor plug is flush with a top surface of the semiconductor layer.

2. The 3D memory device of claim 1 , wherein the memory film does not extend along a top surface and a bottom surface of the channel structure.

3. The 3D memory device of claim 1 , wherein the semiconductor layer comprises single crystalline silicon.

4. The 3D memory device of claim 3 , wherein the semiconductor plug is an epitaxially-grown silicon plug.

5. The 3D memory device of claim 3 , wherein the semiconductor plug is a deposited polysilicon plug or a silicide plug.

6. The 3D memory device of claim 1 , wherein an upper end of the semiconductor channel is in contact with a bottom surface of the semiconductor plug.

7. The 3D memory device of claim 1 , wherein a bottom surface of the semiconductor plug is above a top surface of the memory stack.

8. The 3D memory device of claim 1 , further comprising
a substrate above which the memory stack is disposed; and
a joining interface vertically between the substrate and the memory stack.

9. The 3D memory device of claim 1 , further comprising a peripheral device above the semiconductor layer.

10. The 3D memory device of claim 8 , further comprising a peripheral device vertically between the substrate and the memory stack.

11. A three-dimensional (3D) memory device, comprising:
a first memory deck comprising a first plurality of interleaved conductive layers and dielectric layers;
an etch stop layer on the first memory deck;
a second memory deck comprising a second plurality of interleaved conductive layers and dielectric layers on the etch stop layer;
a channel structure extending vertically through the first and second memory decks and the etch stop layer; and
a semiconductor plug above a top surface of the second memory deck and in contact with the channel structure, wherein a top surface of the semiconductor plug is flush with a top surface of the semiconductor layer.

12. The 3D memory device of claim 11 , wherein the etch stop layer comprises a metal or a semiconductor.

13. The 3D memory device of claim 11 , the channel structure comprises:
a channel plug in a lower portion of the channel structure;
a memory film along a sidewall of the channel structure; and
a semiconductor channel over the memory film and in contact with the channel plug and the semiconductor plug.

14. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising interleaved sacrificial layers and dielectric layers on a front side of a first substrate;
forming a channel hole through the dielectric stack;
forming a memory film and a semiconductor channel along a sidewall and on a bottom surface of the channel hole;
forming a memory stack comprising interleaved conductive layers and dielectric layers by replacing the sacrificial layers in the dielectric stack with the conductive layers;
attaching the first substrate to a second substrate, wherein the front side of the first substrate is toward the second substrate;
thinning the first substrate from a backside of the first substrate to remove parts of the memory film and semiconductor channel on the bottom surface of the channel hole; and
forming a semiconductor plug in the thinned first substrate to contact the semiconductor channel.

15. The method of claim 14 , further comprising, prior to attaching, forming a channel plug in an upper portion of the channel hole to contact the semiconductor channel.

16. The method of claim 14 , wherein forming the semiconductor plug comprises removing parts of the memory film and semiconductor channel in the thinned first substrate to form a recess.

17. The method of claim 16 , wherein forming the semiconductor plug further comprises depositing the semiconductor plug in the recess.

18. The method of claim 16 , wherein forming the semiconductor plug further comprises epitaxially growing the semiconductor plug in the recess from the thinned first substrate.

19. The method of claim 14 , wherein forming the dielectric stack comprises:
forming a first dielectric deck comprising a first plurality of interleaved sacrificial layers and dielectric layers on the frontside of the first substrate;
forming an etch stop layer on the first dielectric deck to cover the first dielectric deck; and
forming a second dielectric deck comprising a second plurality of interleaved sacrificial layers and dielectric layers on the etch stop layer.

20. The method of claim 14 , further comprising:
prior to attaching, forming a peripheral device on the second substrate; or
after forming the semiconductor plug, forming a peripheral device above the thinned first substrate.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Liu Shasha
• Xiao li hong
• Wang Enbo
• Lu Feng
• Xu Qianbin

Classifications

• H01L27/11578

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L23/3114

  Electricity · mapped topic

• H01L27/11551

  Electricity · mapped topic