Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9324727-B2
Application number	US-201414176332-A
Country	US
Kind code	B2
Filing date	Feb 10, 2014
Priority date	Mar 14, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of semiconductor patterns on a substrate, each of the plurality of semiconductor patterns comprising a first region doped with impurities at a first concentration;
a plurality of second regions at a plurality of first upper portions of the substrate, wherein each of the plurality of second regions contacts one of the plurality of semiconductor patterns and is doped with impurities at a second concentration;
a plurality of channel patterns on the plurality of semiconductor patterns, wherein each of the plurality of channel patterns corresponds to a respective one of the plurality of semiconductor patterns and extends in a first direction substantially perpendicular to a top surface of the substrate;
a plurality of gate structures, wherein each of the plurality of gate structures extends in a second direction substantially parallel to the top surface of the substrate and is adjacent to a sidewall of each of one or more of the plurality of channel patterns, and wherein the plurality of gate structures are spaced apart from each other in the first direction;
a plurality of third regions at a plurality of second upper portions of the substrate adjacent to end portions of the plurality of gate structures, wherein each of the plurality of third regions is doped with impurities and is configured to provide a common source line; and
a plurality of fourth regions at a plurality of third upper portions of the substrate between the second and third regions and between adjacent second regions, wherein each of the plurality of fourth regions is doped with impurities at a third concentration, and wherein the third concentration is lower than the first and second concentrations,
wherein the plurality of first and second regions are configured to provide a plurality of vertical channel regions of a plurality of ground selection transistors and the plurality of fourth regions are configured to provide a plurality of horizontal channel regions thereof.

2. The memory device of claim 1 , wherein the impurities of the plurality of fourth regions comprise a first conductive type or a second conductive type.

3. The memory device of claim 1 , wherein a top surface of each of the plurality of semiconductor patterns is coplanar with or lower than a top surface of a lowermost one of the plurality of gate structures in the first direction relative to the top surface of the substrate.

4. The memory device of claim 1 , wherein a top surface of each of the plurality of semiconductor patterns is higher than a top surface of a lowermost one of the plurality of gate structures in the first direction relative to the top surface of the substrate.

5. The memory device of claim 1 , wherein each of the plurality of second regions comprises a first depth from the top surface of the substrate, and each of the plurality of fourth regions comprises a second depth from the top surface of the substrate, wherein the second depth is less deep than the first depth.

6. The memory device of claim 1 , wherein the substrate is doped at a fourth concentration with impurities, wherein the fourth concentration is lower than the first and second concentrations.

7. The memory device of claim 1 , further comprising a plurality of recessed portions of the substrate, wherein each of the plurality of semiconductor patterns extends from a respective one of the plurality of recessed portions.

8. The memory device of claim 1 , wherein the plurality of channel patterns are arranged in a plurality of channel pattern columns which extend in the second direction, and wherein the plurality of channel pattern columns are arranged in a channel pattern array which extends in a third direction which is substantially parallel to the top surface of the substrate and substantially perpendicular to the second direction.

9. The memory device of claim 8 , wherein each of the plurality of gate structures is adjacent to a sidewall of each of the plurality of channel patterns included in at least two of the plurality of channel pattern columns.

10. The memory device of claim 1 ,
wherein a top surface of each of the plurality of semiconductor patterns contacts one of the plurality of channel patterns at a height in the first direction that is remote from the top surface of the substrate, and
wherein a bottom surface of each of the plurality of semiconductor patterns contacts one of the plurality of second regions at the top surface of the substrate.

11. The memory device of claim 1 , wherein a portion of each of the channel patterns overlies a portion of one of the first regions and a portion of one of the second regions in the first direction.

12. A memory device, comprising:
a semiconductor substrate comprising a first concentration of a first conductivity type of impurity;
a plurality of semiconductor patterns on the substrate, each of the plurality of semiconductor patterns comprising a second concentration of the first conductivity type of impurity, wherein the second concentration is greater than the first concentration;
a plurality of channel patterns on the plurality of semiconductor patterns, wherein each of the plurality of channel patterns corresponds to a respective one of the plurality of semiconductor patterns and extends substantially perpendicular to a top surface of the substrate;
a plurality of gate structures, wherein each of the plurality of gate structures extends substantially parallel to the top surface of the substrate;
a plurality of common source lines at the top surface of the substrate, wherein each of the plurality of common source lines is adjacent to end portions of the plurality of gate structures and comprises a second conductivity type of impurity, wherein the second conductivity type of impurity is different from the first conductivity type of impurity; and
a plurality of channel regions at the top surface of the substrate extending between the plurality of semiconductor patterns and the plurality of common source lines and between adjacent semiconductor patterns and comprising a third concentration of impurity, wherein the third concentration is less than the second concentration,
wherein a top surface of each of the plurality of semiconductor patterns contacts one of the plurality of channel patterns at a height that is remote from the top surface of the substrate in a first direction that is perpendicular to the top surface of the substrate.

13. The memory device of claim 12 , wherein the channel regions are first channel regions and the memory device further comprises a plurality of second channel regions at the top surface of the substrate, each of the plurality of second channel regions comprising a fourth concentration of the first conductivity type of impurity and contacting a respective one of the plurality of semiconductor patterns, wherein the fourth concentration is greater than the first concentration and greater than the third concentration.

14. The memory device of claim 12 , wherein each of the plurality of semiconductor patterns extends from a recessed portion of the substrate.

15. The memory device of claim 12 , wherein the top surface of each of the plurality of semiconductor patterns is coplanar with or higher than a top surface of a lowermost one of the plurality of gate structures relative to the top surface of the substrate.

16. The memory device of claim 12 , wherein the top surface of each of the plurality of semiconductor patterns is coplanar with or lower than a bottom surface of a lowermost one of the plurality of gate structures relative to the top

Assignees

• Lee Chang-Hyun
• Kim Hyun-Jung
• Jang Dong-Hoon
• Fayrushin Albert
• Samsung Electronics Co Ltd

Inventors

• Lee Chang-Hyun
• Kim Hyun-Jung
• Jang Dong-Hoon
• Fayrushin Albert

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title