Semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9543316-B2
Application number	US-201514668938-A
Country	US
Kind code	B2
Filing date	Mar 25, 2015
Priority date	Aug 7, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. The vertical channel structures penetrate the stack structure. Conductive pads are disposed on the vertical channel structures. An etch stopper covers sidewalls of the conductive pads. Pad contacts are disposed on the conductive pads to be in contact with the conductive pads. The pad contacts are further in contact with the etch stopper.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
stack structures arranged in a first direction, each of the stack structures including insulating layers and gate electrodes that are alternately and repeatedly stacked on a substrate;
vertical channel structures each penetrating a corresponding one of the stack structures;
conductive pads in contact with the vertical channel structures, each of the conductive pads disposed on a corresponding one of the vertical channel structures; and
an etch stopper covering sidewalls of the conductive pads, exposing top surfaces of the conductive pads, and formed on a top surface of an uppermost insulating layer of the insulating layers of the stack structures,
wherein the etch stopper is an isolated pattern on a corresponding one of the stack structures.

2. The semiconductor memory device of claim 1 , wherein each of the vertical channel structures comprises a tunnel dielectric layer, a charge storage layer, and a vertical channel pattern.

3. The semiconductor memory device of claim 2 , wherein the vertical channel pattern comprises a first vertical channel pattern protruding upwardly from the substrate and a second vertical channel pattern on the first vertical channel pattern, and
wherein the tunnel dielectric layer and the charge storage layer are disposed between the second vertical channel pattern and the stack structures.

4. The semiconductor memory device of claim 1 , wherein the etch stopper has a perimeter in plan view including at least one non-linear side.

5. The semiconductor memory device of claim 1 , wherein the etch stopper comprises silicon nitride.

6. The semiconductor memory device of claim 1 , wherein, for a group of multiple conductive pads of the conductive pads on a stack structure of the stack structures, the etch stopper fills a space between the group of the conductive pads and fills a space from the group of the conductive pads to a perimeter surrounding the group of the conductive pads.

7. The semiconductor memory device of claim 1 , wherein the etch stopper includes a plurality of etch stopper patterns on outer sidewalls of the conductive pads.

8. The semiconductor memory device of claim 1 , further comprising pad contacts in contact with the conductive pads and the etch stopper.

9. A semiconductor memory device, comprising:
stack structures arranged in a first direction, each of the stack structures including insulating layers and gate electrodes that are alternately and repeatedly stacked on a substrate;
vertical channel structures each penetrating a corresponding one of the stack structures;
conductive pads in contact with the vertical channel structures, each of the conductive pads disposed on a corresponding one of the vertical channel structures; and
a trench extending in a second direction crossing the first direction between adjacent ones of the stack structures;
a common source plug in the trench; and
an etch stopper on each of the stack structures, each etch stopper being an isolated pattern horizontally spaced apart from the trench, covering a portion of the conductive pads in the first and second directions, and formed on a top surface of an uppermost insulating layer of the insulating layers of the corresponding one of the stack structures.

10. The semiconductor memory device of claim 9 , wherein each of the vertical channel structures comprises a first vertical channel pattern protruding upwardly from the substrate, a second vertical channel pattern on the first vertical channel pattern, a tunnel dielectric layer, a charge storage layer and a blocking insulating layer, and
wherein the tunnel dielectric layer, the charge storage layer and the blocking insulating layer are disposed between the second vertical channel pattern and the stack structures.

11. The semiconductor memory device of claim 9 , wherein the etch stopper covers sidewalls of the conductive pads and has a perimeter in plan view including at least one non-linear side.

12. The semiconductor memory device of claim 9 , wherein the etch stopper covers top surfaces of the conductive pads and has a linear perimeter in plan view.

13. The semiconductor memory device of claim 9 , further comprising pad contacts in contact with the conductive pads and the etch stopper.

14. The semiconductor memory device of claim 13 , wherein each of the pad contacts is in contact with a top surface and sidewalls of each of the conductive pads and a portion of the etch stopper.

15. The semiconductor memory device of claim 9 , wherein, for a group of multiple conductive pads of the conductive pads on a stack structure of the stack structures, the etch stopper fills a space between the group of the conductive pads and fills a space from the group of the conductive pads to a perimeter surrounding the group of the conductive pads.

16. A device, comprising:
stack structures formed on a semiconductor substrate, the stack structures each including insulating layers and gate electrodes alternately and repeatedly stacked on the semiconductor substrate;
vertical channel structures penetrating the stack structures, each stack structure being penetrated by at least two of the vertical channel structures;
conductive pads each disposed on a corresponding one of the vertical channel structures;
pad contacts each overlying and contacting a corresponding one of the conductive pads; and
etch stoppers each disposed on a corresponding one of the stack structures and covering sidewalls of the conductive pads on the corresponding one of the stack structures, and formed on a top surface of an uppermost insulating layer of the insulating layers of the corresponding one of the stack structures,
wherein adjacent ones of the etch stoppers are spaced apart from each other, and for each of the etch stoppers, the etch stopper extends from the corresponding conductive pads such that a perimeter of the etch stopper in plan view is disposed offset from outer conductive pads of the corresponding conductive pads by a distance.

17. The device of claim 16 , wherein the etch stoppers are in contact with the pad contacts.

18. The device of claim 16 , wherein the pads contacts and the conductive pads are misaligned with each other.

19. The device of claim 16 , wherein some of the vertical channel structures are arranged in a zigzag form in plan view.

20. The semiconductor memory device of claim 1 , further comprising:
a capping insulating layer covering the etch stopper and contacting the conductive pads;
an upper insulating layer formed on the capping insulating layer; and
pad contacts contacting the conductive pads and penetrating the capping insulating layer and the upper insulating layer.

Assignees

• Lee Hyunmin
• Kang Changseok
• Kim Jongwon
• Park Hyeong
• Samsung Electronics Co Ltd

Inventors

• Lee Hyunmin
• Kang Changseok
• Kim Jongwon
• Park Hyeong

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L23/535

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic