Methods and devices for input signal conversion simulation

Patent metadata

Field	Value
Publication number	US-10666277-B2
Application number	US-201916519510-A
Country	US
Kind code	B2
Filing date	Jul 23, 2019
Priority date	Jul 23, 2018
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A method for simulating and optimizing a digital to analog converter is disclosed. The method may include receiving a plurality of digital words. The method may also include determining an effective number of bits, a respective amplitude and a first amplitude correction amount for each digital word. Further, the first amplitude correction amount may be applied to each respective amplitude to generate respective first corrected amplitudes. A timing uncertainty may be determined which may be used to determine a second amplitude correction for each digital word. The second amplitude correction may be applied to each of the respective first corrected amplitudes to generate respective second corrected amplitudes. Next, a representation of an analog signal may be generated based in part on the second corrected amplitudes. Finally, a filter may be applied to the representation of the analog signal and then the representation of the analog signal is outputted.

First claim

What is claimed is:

1. A method for simulating and optimizing a digital to analog converter comprising:
receiving, by a digital analog converter (DAC), a digital signal from a first device, the digital signal including a plurality of digital words;
determining an effective number of bits (ENoB DC ) of the DAC based on a noise associated with the DAC and a hardware bit architecture of the DAC, wherein the noise is related to a bandwidth of the DAC;
determining a respective amplitude for each digital word;
determining, for each digital word, a first amplitude correction amount according to the ENoB DC of the DAC;
applying the first amplitude correction amount to each respective amplitude to generate respective first corrected amplitudes;
determining a sampling rate of the DAC;
applying a multiple of the sampling rate of the DAC to each of the first corrected amplitudes;
determining a timing uncertainty of the DAC;
determining, for each digital word, a second amplitude correction amount based on the timing uncertainty of the DAC;
applying the second amplitude correction amount to each of the respective first corrected amplitudes to generate respective second corrected amplitudes;
generating data indicative of an analog signal based at least in part on the second corrected amplitudes;
applying a filter to the analog signal; and
outputting, by the DAC, the data indicative of the analog signal.

2. The method of claim 1 , wherein each of the plurality of digital words has a resolution about equal to a resolution of the hardware bit architecture of the DAC.

3. The method of claim 1 , wherein the digital signal comprises an electrical signal, an optical signal, a high-resolution digital signal, or a wireless signal.

4. The method of claim 1 , wherein determining the second amplitude correction amount further comprises:
determining a time derivative of the representation of the digital signal; and
multiplying the sample timing uncertainty and the time derivative of the representation of the digital signal to compute the second amplitude correction amount.

5. The method of claim 1 , wherein the digital signal is an oversampled digital signal having an oversampling factor of at least 2.

6. The method of claim 1 , wherein the ENoB of the DAC is characterized by the formula:

ENoB
=

ENoB

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Assignees

• Georgia Tech Res Inst

Inventors

• Varughese Siddharth Jacob
• Langston Jerrod Scott
• Ralph Stephen E
• Thomas Varghese Antony

Classifications

• H03M1/0626 Primary

  by filtering · CPC title

• H04B1/40

  Circuits · CPC title

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G06F9/45508

  Runtime interpretation or emulation, e g. emulator loops, bytecode interpretation · CPC title