Clock skew suppression for time-interleaved clocks

Patent metadata

Field	Value
Publication number	US-10277210-B1
Application number	US-201715794667-A
Country	US
Kind code	B1
Filing date	Oct 26, 2017
Priority date	Oct 26, 2017
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively.

First claim

The invention claimed is:

1. An apparatus, comprising:
circuitry configured to
provide multiple clock components of a sampling clock;
average a pair of the multiple clock components to generate a first averaged signal;
generate a corrected clock component by clipping an amplitude of the first averaged signal; and
interleave corrected clock components for the respective multiple clock components.

2. An apparatus comprising:
circuitry configured to
provide multiple clock components of a sampling clock;
average pairs of the multiple clock components to generate first averaged signals;
average pairs of the first averaged signals to generate second averaged signals;
clip an amplitude of the second averaged signals to generate corrected clock components; and
interleave corrected clock components for the respective multiple clock components.

3. The apparatus of claim 2 , wherein
the multiple clock components of the sampling clock have clock phase skew, and
the circuitry is further configured to
perform the averaging to generate the first averaged signals to convert amplitude mismatch to phase mismatch;
perform the averaging to generate the second averaged signals to convert phase mismatch to amplitude mismatch; and
clip the second averaged signal to eliminate the amplitude mismatch.

4. The apparatus of claim 1 , wherein the clipping performed by the circuitry includes clipping a voltage signal by an amplitude regulator.

5. The apparatus of claim 4 , wherein the amplitude regulator is a CMOS inverter.

6. The apparatus of claim 1 , wherein the circuitry includes a plurality of analog-to-digital converters.

7. The apparatus of claim 6 , wherein the circuitry is further configured to:
sample an analog input for the corrected clock component to provide a sampled analog input;
convert, in the plurality of analog-to-digital converters, sampled analog inputs from the analog signal domain to the digital signal domain in response to the sampling clock to provide digital output segments; and
interleave the digital output segments to produce digital output samples.

8. The apparatus of claim 1 , wherein the circuitry is included in a receiver.

9. The apparatus of claim 1 , wherein the circuitry is included in a transmitter.

10. The apparatus of claim 1 , wherein the circuitry includes a plurality of digital-to-analog converters.

11. The apparatus of claim 10 , wherein the circuitry is further configured to:
sample a digital input for a corresponding corrected clock component generated from the multiple clock components to provide a sampled digital input;
convert, in parallel, the sampled digital inputs from the digital signal domain to the analog signal domain in response to the sampling clock to provide analog output segments; and
interleave the analog output segments to produce digital output samples.

12. A method comprising:
providing multiple clock components of a sampling clock;
averaging a pair of the multiple clock components to generate a first averaged signal;
generating a corrected clock component by clipping an amplitude of the first averaged signal; and
interleave corrected clock components for the respective multiple clock components.

13. The method of claim 12 , further comprising:
converting an analog input to a digital signal.

14. The method of claim 13 , further comprising:
sampling the analog input for a corresponding corrected clock component generated from the multiple clock components to provide a sampled analog input;
converting, in parallel, the sampled analog inputs from the analog signal domain to the digital signal domain in response to the sampling clock to provide digital output segments; and
interleaving the digital output segments to produce digital output samples as the digital signal.

15. The method of claim 12 , further comprising:
converting a digital input to an analog signal.

16. The method of claim 15 , further comprising:
sampling the digital input for a corresponding corrected clock component generated from the multiple clock components to provide a sampled digital input;
converting, in parallel, the sampled digital inputs from the digital signal domain to the analog signal domain in response to the sampling clock to provide analog output segments; and
interleaving the analog output segments to produce analog output samples as the analog signal.

17. The method of claim 12 , further comprising:
driving an interleaved digital-to-analog converter by the interleaved corrected clock components.

18. The method of claim 17 , further comprising clipping a voltage signal by an amplitude regulator.

19. The method of claim 12 , further including averaging pairs of the first averaged signals in order to output a second averaged signal, clipping an amplitude of the second averaged signal, and outputting the clipped second averaged signal as the corrected clock component.

20. The method of claim 19 , wherein the multiple clock components of the sampling clock have clock phase skew, the first averaging converts amplitude mismatch to phase mismatch, and the second averaging converts phase mismatch to amplitude mismatch, and the second averaged signal is clipped to eliminate the amplitude mismatch.

Assignees

• Avago Tech Int Sales Pte Lid
• Avago Technologies General Ip

Inventors

• Rhew Hyo Gyuem
• Garg Adesh
• Nazari Meisam Honarvar
• Zhang Jiawen
• Nazemi Ali
• Cao Jun

Classifications

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H04B1/04

  Circuits · CPC title

• H04B1/16

  Circuits · CPC title

• H03M1/662

  Multiplexed conversion systems · CPC title