Vertical fin type bipolar junction transistor (BJT) device with a self-aligned base contact

Patent metadata

Field	Value
Publication number	US-10658495-B2
Application number	US-201816157928-A
Country	US
Kind code	B2
Filing date	Oct 11, 2018
Priority date	Oct 11, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A method of forming a silicon-germanium heterojunction bipolar transistor (hbt) device is provided. The method includes forming a stack of four doped semiconductor layers on a semiconductor substrate. The method further includes forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers, and removing portions of the second, third, and fourth semiconductor layers to form a vertical fin. The method further includes recessing the second and fourth doped semiconductor layers, and depositing a condensation layer on the second, third, and fourth doped semiconductor layers. The method further includes reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion.

First claim

What is claimed is:

1. A method of forming a silicon-germanium heterojunction bipolar transistor (HBT) device, comprising:
forming a stack of four doped semiconductor layers on a semiconductor substrate;
forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers;
removing portions of the second, third, and fourth semiconductor layers to form a vertical fin;
recessing the second doped semiconductor layer and fourth doped semiconductor layer;
depositing a condensation layer on the exposed surfaces of the second doped semiconductor layer, third doped semiconductor layer, and fourth doped semiconductor layer; and
reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion of the third doped semiconductor layer.

2. The method of claim 1 , wherein the material of the first doped semiconductor layer is silicon, the material of the second doped semiconductor layer is silicon, the material of the third doped semiconductor layer is silicon-germanium, and the material of the fourth doped semiconductor layer is silicon.

3. The method of claim 2 , wherein the first doped semiconductor layer includes an n-type dopant, the second doped semiconductor layer includes an n-type dopant, the third doped semiconductor layer includes a p-type dopant, and the fourth doped semiconductor layer includes an n-type dopant.

4. The method of claim 2 , wherein the condensation layer is germanium oxide (GeO).

5. The method of claim 4 , wherein the protective segment is silicon oxide (SiO).

6. The method of claim 4 , wherein the material of the condensed protruding portion is silicon-germanium (SiGe) with a higher germanium (Ge) concentration than the third doped semiconductor layer.

7. The method of claim 4 , further comprising removing the condensation layer from the second doped semiconductor layer and fourth doped semiconductor layer.

8. The method of claim 7 , further comprising further recessing the second doped semiconductor layer and fourth doped semiconductor layer to form a groove between the protective segment and the second doped semiconductor layer and fourth doped semiconductor layer.

9. The method of claim 8 , further comprising removing at least a portion of the protective segment to expose at least a portion of the condensed protruding portion.

10. A method of forming a silicon-germanium heterojunction bipolar transistor (HBT) device, comprising:
forming a first doped semiconductor layer on a semiconductor substrate;
forming a second doped semiconductor layer on the first doped semiconductor layer, wherein the material of the second doped semiconductor layer is silicon;
forming a third doped semiconductor layer on the second doped semiconductor layer, wherein the material of the third doped semiconductor layer is silicon-germanium;
forming a fourth doped semiconductor layer on the third doped semiconductor layer, wherein the material of the fourth doped semiconductor layer is silicon;
forming a dummy emitter contact and contact spacers on the fourth doped semiconductor layer;
removing portions of the first, second, third, and fourth semiconductor layers to form a vertical fin;
recessing the second doped semiconductor layer and fourth doped semiconductor layer;
depositing a condensation layer on the exposed surfaces of the second doped semiconductor layer, third doped semiconductor layer, and fourth doped semiconductor layer;
reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion of the third doped semiconductor layer; and
removing the condensation layer from the second doped semiconductor layer and fourth doped semiconductor layer.

11. The method of claim 10 , wherein the condensation layer is germanium oxide (GeO).

12. The method of claim 11 , wherein the protective segment is silicon oxide (SiO).

13. The method of claim 12 , wherein the material of the condensed protruding portion is silicon-germanium (SiGe) with a higher germanium (Ge) concentration than the third doped semiconductor layer.

14. The method of claim 13 , wherein the condensation layer has a thickness in a range of about 2 nm to about 6 nm.

Assignees

• IBM

Inventors

• Ok Injo
• Lee Choonghyun
• Seo Soon-Cheon
• Lee Sungjae

Classifications

• H10P95/902

  for the formation of PN junctions without addition of impurities · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/65

  characterised by treatments performed before or after the formation of the materials · CPC title

• H01L29/737 Primary

  Electricity · mapped topic

• H01L21/3242

  Electricity · mapped topic