Bipolar transistor structure and a method of manufacturing a bipolar transistor structure

Patent metadata

Field	Value
Publication number	US-9673294-B2
Application number	US-201615063541-A
Country	US
Kind code	B2
Filing date	Mar 8, 2016
Priority date	Jun 4, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.

First claim

What is claimed is:

1. A method of manufacturing a bipolar transistor structure, the method comprising:
covering a collector region in a substrate with a first dielectric layer structure;
forming a polysilicon layer over the first dielectric layer structure;
forming a second dielectric layer structure over the polysilicon layer, the second dielectric layer structure covering the polysilicon layer;
partially removing the second dielectric layer structure and the polysilicon layer to partially expose the first dielectric layer structure over the collector region and to expose a lateral side of the polysilicon layer;
removing a portion of the polysilicon layer from the exposed lateral side of the polysilicon layer;
removing the exposed first dielectric layer structure to at least partially expose the collector region; and
growing epitaxial silicon over the collector region to form a base region, the epitaxially grown base region connecting to the polysilicon layer.

2. The method of claim 1 ,
wherein growing epitaxial silicon comprises laterally growing polysilicon from the polysilicon layer simultaneously.

3. The method of claim 1 , further comprising:
forming an emitter layer over the epitaxially grown base region.

4. The method of claim 3 , further comprising:
forming a sidewall spacer at the second dielectric layer structure over the epitaxially grown base region before the emitter layer is formed.

5. The method of claim 1 ,
wherein covering the collector region comprises:
forming a first silicon oxide layer over the substrate; and
forming a first silicon nitride layer over the first silicon oxide layer.

6. The method of claim 1 ,
wherein forming the second dielectric layer structure comprises:
forming a second silicon oxide layer over the substrate; and
forming a second silicon nitride layer over the second silicon oxide layer.

7. The method of claim 3 , further comprising:
patterning the emitter layer and the second dielectric layer structure to at least partially expose the polysilicon layer to provide an exposed base terminal electrically contacting the base region.

8. The method of claim 1 , further comprising:
performing an ion implantation after partially removing the second dielectric layer structure and the polysilicon layer to provide a doped collector region.

9. The method of claim 1 , further comprising:
forming two dielectric regions in the substrate next to the collector region before the collector region is covered with the first dielectric layer structure.

10. The method of claim 1 , further comprising:
performing an anneal to electrically link the base region and the polysilicon layer.

11. The method of claim 1 , further comprising:
forming a collector terminal in the substrate electrically contacting the collector region.

12. A method of manufacturing a bipolar transistor structure, the method comprising:
forming a collector region in a substrate;
forming a base region over the collector region,
forming an emitter region over the base region;
forming a base terminal laterally electrically contacting the base region, wherein the base terminal comprises polysilicon; and
forming a dielectric layer structure between the substrate and the base terminal so that substantially all of a surface of the base terminal facing the substrate is disposed on the dielectric layer structure.

13. The method of claim 12 ,
wherein forming the base region comprises epitaxially growing silicon from the collector region.

14. The method of claim 12 ,
wherein the substrate comprises silicon.

15. The method of claim 12 ,
wherein the collector region and the emitter region are formed of silicon doped with a first doping type, and
wherein the base region is formed of silicon doped with a second doping type different from the first doping type.

16. The method of claim 15 ,
wherein the base terminal is formed of silicon doped with the second doping type.

17. The method of claim 12 ,
wherein the base region comprises at least one material of the following group of materials, the group consisting of:
epitaxially grown silicon; and
an epitaxially grown silicon/germanium alloy.

18. The method of claim 12 , further comprising:
forming a dielectric isolation structure in the substrate next to the collector region.

Assignees

• Infineon Technologies Dresden Gmbh

Inventors

• Tschumakow Dmitri Alex
• Dahl Claus
• Tilke Armin

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title