Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures

Patent metadata

Field	Value
Publication number	US-9685564-B2
Application number	US-201615149722-A
Country	US
Kind code	B2
Filing date	May 9, 2016
Priority date	Oct 16, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

First claim

What is claimed:

1. A Gate-All-Around (GAA) Field Effect Transistor (FET) comprising:
a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, and a height that is perpendicular to the horizontal direction, the width of the horizontal nanosheet conductive channel structure defining a physical channel width of the GAA FET;
first and second source/drain regions located at opposing ends of the horizontal nanosheet conductive channel structure; and
a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

2. The GAA FET of claim 1 wherein the horizontal nanosheet conductive channel structure is included in a vertical stack of N horizontal nanosheet conductive channel structures, each of the N horizontal nanosheet conductive channel structures is located in a respective Nth horizontal plane of the GAA FET.

3. The GAA FET of claim 2 wherein each of the N horizontal nanosheet conductive channel structures provides about 1/N of an effective channel width for the GAA FET.

4. The GAA FET of claim 2 wherein each respective horizontal plane is limited to a single horizontal nanosheet conductive channel structure.

5. The GAA FET of claim 2 wherein the unitary gate material extends horizontally between ones of the N horizontal nanosheet conductive channel structures.

6. The GAA FET of claim 2 wherein a respective width of a lowest one of the N horizontal nanosheet conductive channel structures in the vertical stack is greater than a respective width of an uppermost one of the N horizontal nanosheet conductive channel structures in the vertical stack.

7. The GAA FET of claim 2 wherein the unitary gate material seamlessly surrounds each of the N horizontal nanosheet conductive channel structures.

8. The GAA FET of claim 1 wherein the horizontal nanosheet conductive channel structure comprises a first horizontal nanosheet conductive channel structure in a first GAA FET and a second horizontal nanosheet conductive channel structure in a second GAA FET that is directly adjacent to the first GAA FET, and
wherein a space between an edge of the first horizontal nanosheet conductive channel structure and a corresponding edge of the second horizontal nanosheet conductive channel structure is about equal to a Middle-Of-Line (MOL) spacing between directly adjacent source/drain regions of the first and second GAA FETs.

9. The GAA FET of claim 8 wherein the MOL spacing comprises a design rule space for a contact to the unitary gate material between the first and second GAA FETs.

10. The GAA FET of claim 8 wherein the first horizontal nanosheet conductive channel structure is included in a vertical stack of horizontal nanosheet conductive channel structures separated by a vertical spacing such that the MOL spacing is at least twice the vertical spacing.

11. A semiconductor device comprising:
first and second Gate-All-Around (GAA) Field Effect Transistors (FETs) including first and second horizontal nanosheet conductive channel structures, respectively,
wherein the first and second horizontal nanosheet conductive channel structures extend in a shared horizontal plane of the first and second GAA FETs to span first and second channels of the first and second GAA FETs.

12. The semiconductor device of claim 11 wherein a spacing between the first and second horizontal nanosheet conductive channel structures in the shared horizontal plane is about equal to a Middle-Of-Line (MOL) spacing for a contact to a gate material extending between the first and second GAA FETs to the first and second horizontal nanosheet conductive channel structures.

13. The semiconductor device of claim 11 further comprising:
respective first and second source/drain regions located at opposing ends of the horizontal nanosheet conductive channel structure in each of the first and second GAA FETs; and
a gate material completely surrounding the first and second horizontal nanosheet conductive channel structures.

14. The semiconductor device of claim 11 wherein the first and second horizontal nanosheet conductive channel structures are included in a first vertical stack of N horizontal nanosheet conductive channel structures and a second vertical stack of the N horizontal nanosheet conductive channel structures, respectively, each of the N horizontal nanosheet conductive channel structures is located in a respective Nth horizontal plane of the semiconductor device shared by the first and second GAA FETs.

15. The semiconductor device of claim 14 wherein each of the N horizontal nanosheet conductive channel structures provides about 1/N of an effective channel width for one of the first and second GAA FETs.

16. The semiconductor device of claim 14 wherein each respective horizontal plane is limited to a single horizontal nanosheet conductive channel structure of one of the first and second GAA FETs.

17. The semiconductor device of claim 11 wherein first and second widths of the first and second horizontal nanosheet conductive channel structures are different.

18. A semiconductor device comprising:
a Middle-Of-Line (MOL) spacing for a contact from an upper metallization layer to an underlying gate material, the contact extending between first and second directly adjacent Gate-All-Around (GAA) Field Effect Transistors (FETs) that include first and second horizontal nanosheet conductive channel structures, respectively, and the MOL spacing being about equal to an inter-channel spacing between the first and second horizontal nanosheet conductive channel structures in a horizontal direction in the semiconductor device.

19. The semiconductor device of claim 18 wherein the horizontal direction in the first GAA FET includes only the first horizontal nanosheet conductive channel structure and the horizontal direction in the second GAA FET includes only the second horizontal nanosheet conductive channel structure.

20. The semiconductor device of claim 19 further comprising:
a third horizontal nanosheet conductive channel structure in a third GAA FET opposite the second horizontal nanosheet conductive channel structure, wherein an MOL spacing between the first GAA FET and the third GAA FET is equal to about an inter-channel spacing between the first and third GAA FETs.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Sengupta Rwik
• Rodder Mark Stephen
• Hong Joon Goo
• Rakshit Titash

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/021

  of FETs having insulated gates [IGFET] · CPC title

• H10D64/205

  Nanosized electrodes, e.g. nanowire electrodes · CPC title

• H10D62/213

  Channel regions of field-effect devices · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title