Semiconductor package

Patent metadata

Field	Value
Publication number	US-10658350-B2
Application number	US-201816137743-A
Country	US
Kind code	B2
Filing date	Sep 21, 2018
Priority date	Feb 5, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A semiconductor package including a substrate including an external terminal; a first semiconductor chip on the substrate and having a first and a second region; at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and at least one third semiconductor chip on the at least one second semiconductor chip, wherein the first semiconductor chip includes a first pad electrically connected to the at least one second semiconductor chip; a second pad electrically connected to the at least one third semiconductor chip; and a third pad electrically connected to the external terminal, the first pad is on the top surface of the first region, and at least one of the second pad and the third pad is on a top surface of the second region.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate including an external terminal;
a first semiconductor chip on the substrate, the first semiconductor chip having a first region and a second region in a plan view;
at least one second semiconductor chip on the second region of the first semiconductor chip, the at least one second semiconductor chip exposing a top surface of the first region of the first semiconductor chip; and
at least one third semiconductor chip on the at least one second semiconductor chip,
wherein:
the first semiconductor chip includes:
a first pad electrically connected to the at least one second semiconductor chip;
a second pad electrically connected to the at least one third semiconductor chip; and
a third pad electrically connected to the external terminal,

the first pad is on the top surface of the first region, and
at least one of the second pad and the third pad is on a top surface of the second region.

2. The semiconductor package as claimed in claim 1 , wherein:
the first semiconductor chip includes an integrated circuit section therein, and
the first pad and the second pad are electrically connected through the integrated circuit section to the third pad.

3. The semiconductor package as claimed in claim 2 , wherein signals are transmittable to and from the first pad and the second pad through the third pad.

4. The semiconductor package as claimed in claim 1 , further comprising a second connector on the at least one third semiconductor chip, the second connector being coupled to the second pad and a chip pad of the at least one third semiconductor chip,
wherein the second pad is on the top surface of the first region of the first semiconductor chip.

5. The semiconductor package as claimed in claim 1 , further comprising:
a first connection pad on the substrate;
a second connector on the at least one third semiconductor chip, the second connector being coupled to the first connection pad and a chip pad of the at least one third semiconductor chip,
a connection line in the substrate and electrically connected to the first connection pad;
a second connection pad on the substrate and electrically connected to the connection line; and
a third connector on the first semiconductor chip, the third connector being coupled to the second connection pad and the second pad.

6. The semiconductor package as claimed in claim 5 , wherein the second pad is on the top surface of the second region of the first semiconductor chip.

7. The semiconductor package as claimed in claim 1 , further comprising a first connector on a top surface of the at least one second semiconductor chip and coupled to the first pad.

8. The semiconductor package as claimed in claim 1 , further comprising a support structure between the substrate and the at least one second semiconductor chip,
wherein the support structure is spaced apart from the first semiconductor chip.

9. The semiconductor package as claimed in claim 1 , further comprising an encapsulant between the first semiconductor chip and the at least one second semiconductor chip,
wherein the encapsulant exposes the top surface of the first region of the first semiconductor chip.

10. The semiconductor package as claimed in claim 9 , wherein the encapsulant extends onto a side surface of the first semiconductor chip and fills a gap between the substrate and the at least one second semiconductor chip.

11. The semiconductor package as claimed in claim 1 , wherein
the first semiconductor chip includes buffer circuits therein,
the at least one second semiconductor chip includes a memory chip, and
the at least one third semiconductor chip includes a memory chip.

12. The semiconductor package as claimed in claim 1 , wherein:
the at least one second semiconductor chip includes a plurality of stacked second semiconductor chips, and
the first pad is electrically connected to the plurality of stacked second semiconductor chips.

13. The semiconductor package as claimed in claim 1 , wherein:
the at least one third semiconductor chip includes a plurality of stacked third semiconductor chips,
the second pad is electrically connected to the plurality of stacked third semiconductor chips.

14. The semiconductor package as claimed in claim 1 , further comprising a molding layer on the substrate and covering the first semiconductor chip and the at least one second semiconductor chip,
wherein the molding layer covers the first region of the first semiconductor chip and is spaced apart from the top surface of the second region of the first semiconductor chip.

15. A semiconductor package, comprising:
a substrate;
a first semiconductor chip on the substrate and including a first pad, a second pad, and a third pad, the first pad, the second pad, and the third pad being on a top surface of the first semiconductor chip;
at least one second semiconductor chip on the first semiconductor chip, the at least one second semiconductor chip partially exposing the top surface of the first semiconductor chip; and
at least one third semiconductor chip on the at least one second semiconductor chip,
wherein:
the first pad is electrically connected to the at least one second semiconductor chip,
the second pad is electrically connected to the at least one third semiconductor chip,
the third pad is electrically connected to the first pad and the second pad, and
the at least one second semiconductor chip exposes the first pad and covers at least one of the second pad and the third pad.

16. The semiconductor package as claimed in claim 15 , wherein:
the substrate includes an external terminal on a bottom surface thereof, and
the third pad is coupled through the substrate to the external terminal.

17. The semiconductor package as claimed in claim 15 , wherein signals are transmittable to and from the first pad and the second pad through the third pad.

18. The semiconductor package as claimed in claim 15 , further comprising a support structure between the substrate and the second semiconductor chip.

19. The semiconductor package as claimed in claim 15 , wherein
the at least one second semiconductor chip includes a plurality of stacked second semiconductor chips, and
the at least one third semiconductor chip includes a plurality of stacked third semiconductor chips.

20. The semiconductor package as claimed in claim 15 , further comprising:
a first bonding wire on the at least one second semiconductor chip and coupled to the first pad;
a second bonding wire on the at least one third semiconductor chip and coupled to the second pad; and
a third bonding wire on the first semiconductor chip and coupled to the third pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Seonggwan
• Park Chul

Classifications

• H01L2225/06562

  Electricity · mapped topic

• H01L2224/45139

  Electricity · mapped topic

• H01L24/73

  Electricity · mapped topic

• H01L2224/45144

  Electricity · mapped topic

• H01L2924/1434

  Electricity · mapped topic