Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration

Patent metadata

Field	Value
Publication number	US-10651201-B2
Application number	US-201815913530-A
Country	US
Kind code	B2
Filing date	Mar 6, 2018
Priority date	Apr 5, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first conductive pattern in a first conductive layer, the first conductive pattern comprising:
a first segment comprising at least one first point through which a first current is supplied from outside the first conductive pattern,
a second segment comprising at least one second point through which a second current is drawn to outside the first conductive pattern, and
a third segment connecting the first segment to the second segment;

a second conductive pattern in a second conductive layer over the first conductive layer; and
a via electrically connected with the first conductive pattern and the second conductive pattern to allow the first current to be supplied from the first conductive pattern through the via to the second conductive pattern and to allow the second current to be drawn from the second conductive pattern through the via to the first conductive pattern, the via being on the third segment of the first conductive pattern.

2. The integrated circuit of claim 1 , wherein the first current and the second current pass through the via at different times.

3. The integrated circuit of claim 2 , further comprising a standard cell comprising the first conductive pattern,
wherein the first conductive pattern corresponds to an output pin of the standard cell.

4. The integrated circuit of claim 1 , wherein:
the first segment of the first conductive pattern and the second segment of the first conductive pattern extend in a first horizontal direction to be parallel with each other; and
the third segment of the first conductive pattern extends in a second horizontal direction perpendicular to the first horizontal direction.

5. The integrated circuit of claim 4 , wherein the first segment of the first conductive pattern has a stair shape of which a length in the second horizontal direction decreases away from the third segment in the first horizontal direction.

6. The integrated circuit of claim 5 , wherein:
a length of the first segment of the first conductive pattern in the second horizontal direction is determined based on a magnitude of the first current supplied from outside the first conductive pattern and a current per unit width allowed in the first conductive layer; and
the current per unit width allowed in the first conductive layer is determined based on electromigration occurring in the first conductive layer.

7. The integrated circuit of claim 4 , wherein the second segment of the first conductive pattern has a stair shape of which a length in the second horizontal direction decreases away from the third segment in the first horizontal direction.

8. The integrated circuit of claim 7 , wherein:
a length of the second segment of the first conductive pattern in the second horizontal direction is determined based on a magnitude of the second current drawn to outside the first conductive pattern and a current per unit width allowed in the first conductive layer; and
the current per unit width allowed in the first conductive layer is determined based on electromigration occurring in the first conductive layer.

9. The integrated circuit of claim 8 , further comprising a third conductive pattern on the first conductive layer, the third conductive pattern corresponding to an input pin of a standard cell,
wherein at least one segment among the first segment of the first conductive pattern and the second segment of the first conductive pattern has a stair shape of which a length in the second horizontal direction decreases away from the third segment of the first conductive pattern in the first horizontal direction, and
wherein the third conductive pattern is separated from either of the first segment of the first conductive pattern and the second segment of the first conductive pattern in the second horizontal direction.

10. The integrated circuit of claim 9 , wherein the third conductive pattern comprises at least one segment extending in the second horizontal direction and separated in the second horizontal direction from a region, the region having a shortest length in the second horizontal direction in the at least one segment among the first segment of the first conductive pattern and the second segment of the first conductive pattern.

11. The integrated circuit of claim 4 , wherein a length of the third segment of the first conductive pattern in the first horizontal direction is equal to or greater than a length of each of the first segment of the first conductive pattern and the second segment of the first conductive pattern in the second horizontal direction.

12. The integrated circuit of claim 1 , wherein the via, the first conductive layer, and the second conductive layer are formed using a back-end-of-line (BEOL) process for the integrated circuit.

13. An integrated circuit comprising:
a first conductive pattern in a first conductive layer;
a second conductive pattern in a second conductive layer over the first conductive layer; and
a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern to pass through and to allow a second current flowing from the second conductive pattern to the first conductive pattern to pass through,
wherein the via is on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

14. The integrated circuit of claim 13 , wherein:
the first conductive pattern comprises:
a first segment comprising at least one first point through which the first current is supplied from outside the first conductive pattern,
a second segment comprising at least one second point through which the second current is drawn to outside the first conductive pattern, and
a third segment connecting the first segment of the first conductive pattern and the second segment of the first conductive pattern; and

the via is on the third segment of the first conductive pattern.

15. The integrated circuit of claim 14 , wherein:
the first segment of the first conductive pattern and the second segment of the first conductive pattern extend in a first horizontal direction to be parallel with each other; and
the third segment of the first conductive pattern extends in a second horizontal direction perpendicular to the first horizontal direction.

16. The integrated circuit of claim 15 , further comprising a standard cell comprising the first conductive pattern,
wherein the first conductive pattern corresponds to an output pin of the standard cell.

17. The integrated circuit of claim 15 , wherein a length of the third segment of the first conductive pattern in the first horizontal direction is equal to or greater than a length of each of the first segment of the first conductive pattern and the second segment of the first conductive pattern in the second horizontal direction.

18. The integrated circuit of claim 15 , wherein at least one segment among the first segment of the first conductive pattern and the second segment of the first conductive pattern has a stair shape of which a length in the second horizontal direction decreases away from the third segment of the first conductive pattern in the first horizontal direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ha-Young
• Kim Chang-Beom
• Roh Hyun-Jeong
• Song Tae-Joong
• Lee Dal-Hee
• Cho Sung-We

Classifications

• H01L2027/11864

  Electricity · mapped topic

• H01L2027/11885

  Electricity · mapped topic

• H01L27/11807 Primary

  Electricity · mapped topic

• H01L2027/11861

  Electricity · mapped topic

• H01L2027/11875

  Electricity · mapped topic