Processing circuitry

Patent metadata

Field	Value
Publication number	US-10649732-B2
Application number	US-201816050990-A
Country	US
Kind code	B2
Filing date	Jul 31, 2018
Priority date	Jul 31, 2018
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (SC1, SC2) respectively, and generate respective first and second PWM signals (SPWM1, SPWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (SC1) corresponds to a sum of a first and second input signals (S1, S2) and the second combined signal (SC2) corresponds to the difference between the first and second input signals (S1, S2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D1, D2) based on a parameter related to the frequency of the respective first or second PWM signal. A subtractor (105) determine a difference between the first and second count values (D1, D2) and provides an output signal (DOUT) based on this difference.

First claim

The invention claimed is:

1. A processing circuit comprising:
a first time-encoding modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first pulse-width-modulation (PWM) signal with a cycle frequency that depends substantially on the square of the value of the first combined signal;
a second time-encoding modulator configured to receive a second combined signal corresponding to a difference between said first input signal and said second input signal and to generate a second PWM signal with a cycle frequency that depends substantially on the square of the value of the second combined signal;
a first time-decoding converter configured to receive the first PWM signal and to provide a first count value based on a first parameter of the first PWM signal;
a second time-decoding converter configured to receive the second PWM signal and to provide a second count value based on a second parameter of the second PWM signal; and
a subtractor configured to determine a difference between the first and second count values and to output an output signal based on said difference between the first and second count values;
wherein the first time-decoding converter and the second time-decoding converter each comprise a counter configured to receive a reference clock signal and count a number of PWM cycles in each of a succession of count periods defined by the reference clock signal to provide the respective first or second count value.

2. A processing circuit according to claim 1 , wherein the first parameter is a PWM cycle frequency of the first PWM signal and the second parameter is a PWM cycle frequency of the second PWM signal.

3. A processing circuit according to claim 1 , wherein the first parameter is a PWM cycle period of the first PWM signal and the second parameter is a PWM cycle period of the second PWM signal.

4. A processing circuit according to claim 1 wherein the first and second time-decoding converters each comprise a respective counter configured to receive a reference clock signal and wherein the processing circuit is selectively operable in a first mode or a second mode, wherein:
in the first mode of operation the first and second parameters are PWM cycle frequencies of the first and second PWM signals respectively, and the counters of the first and second time-decoding converters are each configured count a number of PWM cycles in each of a succession of count periods defined by the reference clock signal to provide the count value;
in the second mode of operation the first and second parameters are PWM cycle periods of the first and second PWM signals respectively, and the counters of the first and second time-decoding converters are each configured count a number of cycles of the reference clock signal in a PWM cycle period defined by the respective one of the first or second PWM signals to provide the count value; and
the frequency of the reference clock signal is greater in the second mode than in the first mode.

5. A processing circuit according to claim 1 further comprising a signal combiner having a first combiner element configured to additively combine the first input signal and the second input signal to generate the first combined signal and a second combiner element configured to subtractively combine the first input signal and the second input signal to generate the second combined signal.

6. A processing circuit according to claim 5 wherein:
the first combiner element comprises first and second current sources configured to provide currents defined by the first and second input signals respectively, wherein the first and second current sources are configured to supply current of the same polarity as one another to an output node of the first combiner element; and
the second combiner element comprises third and fourth current sources configured to provide currents defined by the first and second input signals respectively, wherein the third and fourth current sources are configured to supply current of the opposite polarity as one another to an output node of the second combiner element.

7. A processing circuit according to claim 1 implemented as an integrated circuit.

8. An electronic device comprising a processing circuit according to claim 1 .

9. An electronic device as claimed in claim 8 wherein the device is at least one of: a battery powered device; a portable device; a communications device; a mobile telephone; a smartphone; a computing device; a laptop; notebook or tablet computer; a gaming device; a personal media player; a wearable device; a voice controlled device.

10. A processing circuit comprising:
a first time-encoding modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first pulse-width-modulation (PWM) signal with a cycle frequency that depends substantially on the square of the value of the first combined signal;
a second time-encoding modulator configured to receive a second combined signal corresponding to a difference between said first input signal and said second input signal and to generate a second PWM signal with a cycle frequency that depends substantially on the square of the value of the second combined signal;
a first time-decoding converter configured to receive the first PWM signal and to provide a first count value based on a first parameter of the first PWM signal;
a second time-decoding converter configured to receive the second PWM signal and to provide a second count value based on a second parameter of the second PWM signal; and
a subtractor configured to determine a difference between the first and second count values and to output an output signal based on said difference between the first and second count values;
wherein the first time-decoding converter and the second time-decoding converter each comprise a counter configured to receive a reference clock signal and to count a number of cycles of the reference clock signal in a PWM cycle period defined by the respective one of the first or second PWM signals to provide the respective first or second count value.

11. A processing circuit according to claim 10 wherein the processing circuit is configured such the value of each of the first and second combined signals is limited to be no greater than a defined limit, such that a maximum variation in cycle frequency of the respective first or second PWM signals is no greater than 25%.

12. A processing circuit comprising:
a first time-encoding modulator configured to receive a first combined signal corresponding to a sum of a first input signal and a second input signal and to generate a first pulse-width-modulation (PWM) signal with a cycle frequency that depends substantially on the square of the value of the first combined signal;
a second time-encoding modulator configured to receive a second combined signal corresponding to a difference between said first input signal and said second input signal and to generate a second PWM signal with a cycle frequency that depends substantially on the square of the value of the second combined signal;
a first time-decoding converter configured to receive the first PWM signal and to provide a first count value based on a first parameter of the first PWM signal;
a second time-decoding converter configured to receive the second PWM signal and to provide a second count value based on a second parameter of the second PWM signal; and
a subtractor configured to determine a difference between the first and second count values and to output an output signal based on said difference betwe

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Lesso John Paul
• Mccloy-Stevens Mark

Classifications

• G06F7/5235

  using indirect methods, e.g. quarter square method, via logarithmic domain · CPC title

• G06F7/5338 Primary

  each bitgroup having two new bits, e.g. 2nd order MBA · CPC title

• H03M1/508 Primary

  the pulse width modulator being of the self-oscillating type · CPC title

• H03K19/1772

  with synchronous operation of at least one of the logical matrixes · CPC title

• G06F7/53

  in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence) · CPC title