Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices

Patent metadata

Field	Value
Publication number	US-10644156-B2
Application number	US-201815919079-A
Country	US
Kind code	B2
Filing date	Mar 12, 2018
Priority date	Mar 12, 2018
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

First claim

What is claimed is:

1. A method, comprising:
forming a fin disposed on a semiconductor substrate;
forming a dummy gate disposed over said fin, wherein said dummy gate has a top at a first height above said semiconductor substrate;
forming an interlayer dielectric (ILD) feature disposed over and in physical contact with said fin and adjacent said dummy gate, wherein said ILD has a top at a second height above said semiconductor substrate, and wherein the second height is below the first height;
capping said ILD with a dielectric cap, wherein the dielectric cap has a top at the first height;
replacing said dummy gate with a gate stack comprising a metal gate electrode and a nitride cap;
removing said dielectric cap and the ILD, to yield a trench; and
filling said trench with a contact metal, wherein filling the trench with the contact metal comprises overfilling the trench with the contact metal and performing chemical-mechanical polishing (CMP) to reduce a top of the contact metal to the first height.

2. The method of claim 1 , wherein forming said ILD feature comprises forming the ILD to have the top at the first height and recessing the top of the ILD to the second height.

3. The method of claim 1 , wherein capping said ILD with a dielectric cap comprises capping said ILD with a dielectric cap that comprises silicon carbon oxide (SiOC).

4. The method of claim 3 , wherein capping said ILD comprises depositing SiOC over said fin, said dummy gate, and said ILD; depositing an oxide over the SiOC, chemical-mechanical polishing (CMP) the oxide and the SiOC to the first height, and performing a non-selective etch to remove oxide.

5. The method of claim 1 , wherein the contact metal is selected from the group consisting of tungsten, copper, and cobalt.

6. The method of claim 1 , wherein replacing said dummy gate with said gate stack comprises forming the gate stack such that the top of the dielectric cap is less than 5 nm below the top of the nitride cap.

7. A system, comprising:
a semiconductor device processing system to manufacture a semiconductor device; and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of the semiconductor device processing system;
wherein the semiconductor device processing system is adapted to:
provide a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the semiconductor substrate; and an interlayer dielectric (ILD) disposed over and in physical contact with the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the semiconductor substrate, wherein the second height is below the first height;
cap the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height;
replace said dummy gate with a gate stack comprising a metal gate electrode and a nitride cap;
remove said dielectric cap and the ILD, to yield a trench; and
fill said trench with a contact metal, wherein to fill the trench with the contact metal, the semiconductor device processing system is adapted to overfill the trench with the contact metal and perform chemical-mechanical polishing (CMP) to reduce a top of the contact metal to the first height.

8. The system of claim 7 , wherein the semiconductor device processing system is adapted to form the ILD to have the top at the first height and recess the top of the ILD to the second height.

9. The system of claim 7 , wherein the semiconductor device processing system is adapted to form the dielectric cap from silicon carbon oxide (SiOC).

10. The system of claim 9 , wherein the semiconductor device processing system is adapted to cap the ILD by depositing SiOC over aid fin, said dummy gate, and said ILD; depositing an oxide over the SiOC, chemical-mechanical polishing (CMP) the oxide and the SiOC to the first height, and performing a non-selective etch to remove oxide.

11. The system of claim 7 , wherein the semiconductor device processing system is adapted to form the contact metal from tungsten or cobalt.

12. The system of claim 7 , wherein, after the semiconductor device processing system replaces the dummy gate with the gate stack, the top of the dielectric cap is less than 5 nm below the top of the nitride cap.

Assignees

• Globalfoundries Inc

Inventors

• Gao Jinsheng
• Jaeger Daniel
• Aquilino Michael
• Carpenter Patrick
• Wu Xusheng
• Huang Haigou

Classifications

• H01L29/42392

  Electricity · mapped topic

• H01L21/823828

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic