Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device

Patent metadata

Field	Value
Publication number	US-10418455-B2
Application number	US-201715716287-A
Country	US
Kind code	B2
Filing date	Sep 26, 2017
Priority date	Sep 26, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

First claim

What is claimed is:

1. A method, comprising:
forming a plurality of fins on a semiconductor substrate;
forming, over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion;
forming, over a second portion of the fins, a gate region;
forming a trench in a portion of the gate region;
forming a first oxide layer at a bottom region of the trench;
depositing, prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material into the trench for forming a second oxide layer, the second oxide layer comprising the flowable oxide and the first oxide layer, the second oxide layer having a first height; and
performing the amorphous-silicon (a-Si) deposition process.

2. The method of claim 1 , further comprising:
performing a replacement metal gate (RMG) process in the gate region;
performing a oxide chemical-mechanical polishing (CMP) process over the flowable oxide; and
performing an oxide recess process to remove the flowable oxide from gate region portions outside the trench.

3. The method of claim 2 , wherein performing the oxide recess process comprises performing at least one of a dry reactive-ion etching (RIE), or a wet etch process.

4. The method of claim 1 , further comprising:
performing an a-Si chemical-mechanical polishing (CMP) process; and
performing an a-Si etch back process to recess the a-Si, wherein the oxide layer at the bottom region of the trench substantially prevents residue at the bottom region of the trench.

5. The method of claim 1 , further comprising:
performing a trench silicide (TS) process for forming a TS contact.

6. The method of claim 5 , wherein forming the TS contact comprises:
depositing a hard mask layer over the gate region outside the trench;
performing a TS lithography process;
performing an a-Si etch process for removing a portion of the a-Si material;
depositing a low-k material into the trench; and
performing a chemical-mechanical polishing (CMP) process on the low-k material.

7. The method of claim 1 , wherein forming the gate region comprises:
forming a poly gate material layer;
forming a nitride liner adjacent the poly gate material layer;
forming a gate spacer adjacent the nitride liner; and
forming an oxide liner adjacent the gate space.

8. The method of claim 2 , wherein performing the RMG process comprises:
performing a poly pull process in the gate region;
depositing a work function metal layer in the gate region;
depositing a gate metal in the gate region; and
performing a chemical-mechanical polishing (CMP) process on the gate metal.

9. The method of claim 8 , wherein depositing the gate metal comprises depositing at least one of a tungsten material, or cobalt material.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Jaeger Daniel
• Huang Haigou
• Basker Veeraraghavan
• Nassar Christopher
• Gao Jinsheng
• Aquilino Michael

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P32/1414

  the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P14/2923

  being conductive materials, e.g. metallic silicides · CPC title

• H10D64/0131

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title