Method of forming contact useful in replacement metal gate processing and related semiconductor structure

Patent metadata

Field	Value
Publication number	US-9337094-B1
Application number	US-201514589222-A
Country	US
Kind code	B1
Filing date	Jan 5, 2015
Priority date	Jan 5, 2015
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A method of forming a contact is provided. The method may include forming a liner against a spacer around a gate; selectively removing an upper portion of the liner adjacent the spacer, forming a void; forming a spacer extension by filling the void with a spacer material; and forming a contact self-aligned to the spacer extension. A semiconductor structure is also disclosed. The structure may include: a gate; a spacer around the gate; a spacer extension extending laterally from an upper portion of the spacer; and a contact self-aligned to the spacer extension.

First claim

What is claimed is:

1. A method of forming a contact, comprising:
forming a liner against a spacer around a gate;
selectively removing an upper portion of the liner adjacent the spacer, forming a void;
forming a spacer extension by filling the void with a spacer material; and
forming a contact self-aligned to the spacer extension.

2. The method of claim 1 , wherein the liner extends over a first interlayer dielectric (ILD) layer, further comprising forming a second ILD layer over the liner, wherein the second ILD layer is more polishing resistant than the first ILD layer.

3. The method of claim 2 , wherein forming the second ILD layer includes forming a high density plasma (HDP) oxide layer over the liner.

4. The method of claim 2 , wherein forming the liner includes forming the liner between a plurality of gates over the first ILD layer.

5. The method of claim 1 , wherein the liner includes one of a high dielectric constant dielectric and titanium nitride (TiN).

6. The method of claim 1 , wherein the gate includes a dummy gate, further comprising, prior to the selective removing:
removing the dummy gate; and
forming a metal gate in place of the dummy gate.

7. A method, comprising:
forming a liner against a spacer around a dummy gate;
removing the dummy gate;
forming a metal gate in place of the dummy gate;
selectively removing an upper portion of the liner adjacent the spacer, forming a void;
forming a spacer extension by filling the void with a spacer material; and
forming a contact self-aligned to the spacer extension.

8. The method of claim 7 , wherein the liner extends over a first interlayer dielectric (ILD) layer over a substrate, further comprising forming a second ILD layer over the liner, wherein the second ILD layer is more polishing resistant than the first ILD layer.

9. The method of claim 8 , wherein the second ILD layer forming includes forming a high density plasma (HDP) oxide layer over the liner.

10. The method of claim 8 , wherein the liner forming includes forming the liner between a plurality of gates over the first ILD layer.

11. The method of claim 7 , wherein the liner includes one of a high dielectric constant dielectric and titanium nitride (TiN).

12. A semiconductor structure comprising:
a gate;
a spacer around the gate;
a spacer extension extending laterally from an upper portion of the spacer;
a contact self-aligned to the spacer extension, and
a liner extending below the spacer extension.

13. The semiconductor structure of claim 12 , wherein the liner extends laterally from the spacer.

14. The semiconductor structure of claim 13 , further comprising a first interlayer dielectric (ILD) layer above a second ILD layer over a substrate, wherein the first ILD layer is more polishing resistant than the second ILD layer, and wherein the liner extends laterally between the first ILD layer and the second ILD layer.

15. The semiconductor structure of claim 14 , wherein the first ILD layer includes a high density plasma (HDP) oxide and the second ILD layer includes a flowable chemical vapor deposition (FCVD) oxide layer.

16. The semiconductor structure of claim 12 , wherein the gate includes a first gate positioned over a fin over a substrate and a second gate positioned on the substrate, and
wherein the liner extends laterally from the spacer of the first gate to the spacer of the second gate.

17. The semiconductor structure of claim 12 , wherein the spacer extension includes a ledge extending from the spacer.

18. The semiconductor structure of claim 12 , wherein the spacer and the spacer extension include a nitride.

19. The semiconductor structure of claim 12 , wherein the gate includes a metal gate.

Assignees

• IBM

Inventors

• Pranatharthiharan Balasubramanian
• Ok Injo
• Surisetty Charan V V S

Classifications

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title