Display device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10644089-B2
Application number	US-201715611482-A
Country	US
Kind code	B2
Filing date	Jun 1, 2017
Priority date	Oct 26, 2016
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A display device includes a scan line that extends in a first direction on a substrate and that transmits a scan signal; a data line that extends in a second direction that intersects the first direction and that transmits a data signal; a driving voltage line that extends in the second direction and that transmits a driving voltage; a transistor that includes a second transistor connected to the scan line and the data line and a first transistor connected to the second transistor; a light emitting device connected to the transistor; and a conductive pattern disposed between the substrate and the first transistor, where each of the first and second transistors includes an active pattern with a stacked first semiconductor layer and a second semiconductor layer, which have different crystalline states.

First claim

What is claimed is:

1. A display device comprising:
a scan line that extends in a first direction on a substrate, wherein the scan line transmits a scan signal;
a data line that extends in a second direction that intersects the first direction, wherein the data line transmits a data signal;
a driving voltage line that extends in the second direction, wherein the driving voltage line transmits a driving voltage;
a second transistor connected to the scan line and the data line;
a first transistor connected to the second transistor;
a light emitting device connected to the first transistor;
a first conductive pattern disposed on-the substrate; and
a second conductive pattern disposed on the first transistor and provided on the same layer as the scan line,
wherein each of the first and second transistors includes an active pattern with a stacked first semiconductor layer and a second semiconductor layer, which have different crystalline states,
wherein the first conductive pattern is disposed under the active pattern of the first transistor with an insulating layer interposed therebetween, and
wherein the second conductive pattern is disposed on the active pattern of the first transistor and overlaps at least a portion of the active pattern of the first transistor.

2. The display device of claim 1 , wherein the first semiconductor layer is disposed under the second semiconductor layer and has a smaller crystalline particle than the second semiconductor layer.

3. The display device of claim 1 , further comprising a storage capacitor between the substrate and the first semiconductor layer, wherein the storage capacitor includes the first conductive pattern, a metal layer that overlaps the first conductive pattern, and the insulating layer interposed therebetween.

4. The display device of claim 1 , wherein the first conductive pattern is a light blocking layer that blocks light incident into a bottom surface of the substrate.

5. The display device of claim 1 , further comprising an auxiliary power line integrally formed with the conductive pattern, and an initialization power line that extends in the first direction.

6. The display device of claim 3 , wherein the first transistor includes:
a gate electrode integrally formed with the metal layer;
the active pattern disposed on the gate electrode; and
source and drain electrodes each connected to respective ends of the active pattern.

7. The display device of claim 1 , further comprising a storage capacitor that includes a lower electrode disposed on the active pattern, an upper electrode that overlaps the lower electrode, and an interlayer insulating layer interposed therebetween,
wherein the interlayer insulating layer is disposed on the insulating layer.

8. The display device of claim 7 , wherein the upper electrode is integrally formed with the driving voltage line, and the lower electrode is integrally formed with the second conductive pattern.

9. The display device of claim 7 , wherein the first transistor includes:
a gate electrode integrally formed with the conductive pattern;
the active pattern disposed on the gate electrode; and
source and drain electrodes each connected to respective ends of the active pattern.

10. A display device comprising:
a second transistor on a substrate that is connected to a scan line and a data line;
a first transistor on the substrate that is connected to the second transistor;
a light emitting device connected to the first transistor;
a first conductive pattern disposed on the substrate;
a second conductive pattern disposed on the first transistor and provided on the same layer as the scan line,
wherein each of the first and second transistors includes an active pattern with a stacked first semiconductor layer and a second semiconductor layer, which have different crystalline states,
wherein the first semiconductor layer is disposed under the second semiconductor layer and has a smaller crystalline particle than the second semiconductor layer, and
wherein the first conductive pattern is a light blocking layer that blocks light incident into a bottom surface of the substrate,
wherein the first conductive pattern is disposed under the active pattern of the first transistor with an insulating layer interposed therebetween, and
wherein the second conductive pattern is disposed on the active pattern of the first transistor and overlaps at least a portion of the active pattern of the first transistor.

11. The display device of claim 10 , further comprising:
a storage capacitor between the substrate and the first semiconductor layer, wherein the storage capacitor includes the first conductive pattern, a metal layer that overlaps the first conductive pattern, and the insulating layer interposed therebetween,
wherein the first transistor includes;
a gate electrode integrally formed with the metal layer;
the active pattern disposed on the gate electrode; and

source and drain electrodes each connected to respective ends of the active pattern.

12. The display device of claim 10 , further comprising:
a storage capacitor that includes a lower electrode disposed on the active pattern, an upper electrode that overlaps the lower electrode, and an interlayer insulating layer interposed therebetween,
wherein the lower electrode is integrally formed the second conductive pattern,
wherein the first transistor includes:
a gate electrode integrally formed with the first conductive pattern;
the active pattern disposed on the gate electrode; and

source and drain electrodes each connected to respective ends of the active pattern,
wherein the interlayer insulating layer is disposed on the insulating layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Jun Hee
• Bae In Jun
• Ebisuno Kohei

Classifications

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3241

  the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title